Method and system for automatic generation of instruction-set documentation from an abstract processor model described using a hierarchical architectural description language

• US 8,006,225 B1
• Filed: 06/03/2005
• Issued: 08/23/2011
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synposys Incorporated
• Inventors: Hoffmann, Andreas, Greive, Volker, Braun, Gunnar
• Primary Examiner(s): Kendall; Chuck O
• Application Number:
  US11/145,240
• Time in Patent Office: 2,272 Days
• Field of Search: None
• US Class Current: 717/106
• CPC Class Codes: G06F 8/73 Program documentation

Abstract

A method and system for the automatic generation of instruction-set manuals. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the abstract processor model. The flattening process generates a plurality of rules grouped by common convergent instructions. Each rule describes an instruction path through the hierarchical structure that converges at a corresponding convergent instruction. An instruction-set documentation is automatically generated from the plurality of rules, wherein the instruction-set documentation is arranged convergent instruction by convergent instruction.

Claims

1. A method for automatic generation of instruction-set manuals, comprising:

accessing an abstract processor model of a processor, wherein said abstract processor model is described using a hierarchical architecture description language (ADL), wherein said abstract processor model comprises a plurality of instructions arranged in a hierarchical structure;

generating an internal representation of said abstract processor model by flattening said abstract processor model to obtain a plurality of rules grouped by common convergent instructions, wherein each rule describes an instruction path through said hierarchical structure that converges at a corresponding convergent instruction; and

automatically generating an instruction-set documentation for said processor from said internal representation, wherein said instruction-set documentation is arranged convergent instruction by convergent instruction.

2. The method of claim 1, wherein said flattening said abstract processor model further comprises:

determining all permutations of instruction combinations in said abstract processor model; and

categorizing said permutations into separate groups which have the same convergent instruction.

3. The method of claim 1, wherein said automatically generating an instruction-set further comprises:

converting each of said plurality of rules that is flattened and associated with a convergent instruction into a back-end format of said instruction-set documentation.

4. The method of claim 1, wherein said automatically generating an instruction-set documentation further comprises:

for a convergent instruction, accessing coding information as an extension of said abstract processor model, wherein said coding information comprises binary information of said convergent instruction; and

listing said coding description in said instruction-set documentation for said convergent instruction.

5. The method of claim 1, wherein said automatically generating an instruction-set documentation further comprises:

for a convergent instruction, accessing syntax information as an extension of said convergent instruction in said abstract processor model, wherein said syntax information comprises assembly information of said convergent instruction; and

listing said syntax information in said instruction-set documentation for said convergent instruction.

6. The method of claim 1, wherein said automatically generating an instruction-set documentation further comprises:

for a convergent instruction, accessing documentation information as an extension of said convergent instruction in said abstract processor model, wherein said documentation information comprises textual information describing said convergent instruction; and

listing said documentation information in said instruction-set documentation for said convergent instruction.

7. The method of claim 6, further comprising:

before said flattening, marking each convergent instruction in said hierarchical structure with a documentation section, wherein said documentation section describes an instruction of a corresponding instruction node.

8. The method of claim 1, wherein said automatically generating an instruction-set documentation further comprises:

for a convergent instruction, accessing semantical information as an extension of said convergent instruction in said abstract processor model; and

listing operations in said semantical information in said instruction-set documentation for said convergent instruction.

9. A system for automatic generation of instruction-set manuals, comprising:

an accessing module for accessing an abstract processor model of a processor, wherein said abstract processor model is described using a hierarchical architecture description language (ADL), wherein said abstract processor model comprises a plurality of instructions arranged in a hierarchical structure;

a flattening module for generating an internal representation of said instruction-set description by flattening said abstract processor model arranged to obtain a plurality of rules grouped by common convergent instructions, wherein each rule describes an instruction path through said hierarchical structure that converges at a corresponding convergent instruction; and

a document generator for automatically generating an instruction-set documentation for said processor from said internal representation, wherein said instruction-set documentation is arranged convergent instruction by convergent instruction.

10. The system of claim 9, wherein said abstract processor model represents an instruction-set description of said processor.

11. The system of claim 9, wherein said abstract processor model comprises a hierarchical operation tree.

12. The system of claim 9, wherein said document generator further comprises:

a translator for translating a convergent instruction in said internal representation to a back-end format of said instruction-set documentation.

13. The system of claim 12, wherein said back-end format is taken from a group consisting essentially of:

hypertext markup language (html);

postscript;

portable document format (pdf); and

latex.

14. The system of claim 9, wherein each convergent instruction described in said instruction-set documentation further comprises:

coding information comprising binary information of said convergent instruction;

syntax information comprising assembly information for said convergent instruction; and

documentation information comprising textual information describing said convergent instruction.

15. The system of claim 9, wherein each convergent instruction described in said instruction-set documentation further comprises:

semantical information comprising micro-operations of said convergent instruction.

16. A computer system comprising:

a processor; and

a computer readable memory coupled to said processor and containing program instructions that, when executed, implement a method for automatic generation of instruction-set manuals, comprising;

accessing an abstract processor model of a processor, wherein said abstract processor model is described using a hierarchical architecture description language (ADL), wherein said abstract processor model comprises a plurality of instructions arranged in a hierarchical structure;

generating an internal representation of said abstract processor model by flattening said abstract processor model to obtain a plurality of rules grouped by common convergent instructions, wherein each rule describes an instruction path through said hierarchical structure that converges at a corresponding convergent instruction; and

automatically generating instruction-set documentation for said processor from said internal representation, wherein said instruction-set documentation is arranged convergent instruction by convergent instruction.

17. The computer system of claim 16, wherein said flattening said abstract processor model further comprises:

determining all permutations of instruction combinations in said abstract processor model; and

categorizing said permutations into separate groups which have the same convergent instruction.

18. The computer system of claim 16, wherein said automatically generating instruction-set further comprises:

converting each of said plurality of rules that is flattened and associated with a convergent instruction into a back-end format of said instruction-set documentation.

19. The computer system of claim 16, wherein said automatically generating instruction-set documentation further comprises:

for a convergent instruction, accessing coding information as an extension of said abstract processor model, wherein said coding information comprises binary information of said convergent instruction; and

listing said coding description in said instruction-set documentation for said convergent instruction.

20. The computer system of claim 16, wherein said automatically generating instruction-set documentation further comprises:

for a convergent instruction, accessing syntax information as an extension of said convergent instruction in said abstract processor model, wherein said syntax information comprises assembly information of said convergent instruction; and

listing said syntax information in said instruction-set documentation for said convergent instruction.

21. The computer system of claim 16, wherein said automatically generating instruction-set documentation further comprises:

for a convergent instruction, accessing documentation information as an extension of said convergent instruction in said abstract processor model, wherein said documentation information comprises textual information describing said convergent instruction; and

listing said documentation information in said instruction-set documentation for said convergent instruction.

22. The computer system of claim 21, further comprising:

before said flattening, marking each convergent instruction in said hierarchical structure with a documentation section, wherein said documentation section describes an instruction of a corresponding instruction node.

23. The computer system of claim 16, wherein said automatically generating instruction-set documentation further comprises:

for a convergent instruction, accessing semantical information as an extension of said convergent instruction in said abstract processor model; and

listing operations in said semantical information in said instruction-set documentation for said convergent instruction.