Methods for fabricating contacts to pillar structures in integrated circuits

• US 8,008,095 B2
• Filed: 10/03/2007
• Issued: 08/30/2011
• Est. Priority Date: 10/03/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Costrini, Gregory, Rooks, Michael J., Sun, Jonathan Zanhong, Assefa, Solomon, Jahnes, Christopher Vincent
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US11/866,455
• Publication Number:
  US 20090091037A1
• Time in Patent Office: 1,427 Days
• Field of Search: 438/637, 438/618, 438/3, 365/164
• US Class Current: 438/3
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.

Claims

1. A method of forming a pillar structure that is contacted by a vertical contact in an integrated circuit, the method comprising the steps of:

sequentially depositing pillar structure material layers, a hard mask layer and a hard mask cap layer on a substrate;

patterning the hard mask cap and hard mask layers to form a hard mask cap and a hard mask on the pillar structure material layers, the hard mask comprising carbon;

utilizing the hard mask cap and the hard mask to pattern at least a portion of the pillar structure material layers to form a pillar structure;

depositing a liner on the hard mask cap, hard mask and pillar structure;

forming a lower dielectric layer in contact with a side portion of the liner;

depositing a stop layer on top of the lower dielectric layer and a portion of the liner disposed above the hard mask cap, hard mask and pillar structure;

forming an upper dielectric layer on top of the stop layer;

forming a trench in the upper dielectric layer down to the stop layer;

removing the stop layer and the liner and the hard mask cap selectively to exposed surfaces of the lower and upper dielectric layers and the hard mask to expose an upper surface of the hard mask;

removing the hard mask; and

depositing a conductive material into the trench and a region previously occupied by the hard mask to form the vertical contact and a conductive line.

2. The method of claim 1, wherein the hard mask comprises diamond-like carbon.

3. The method of claim 1, wherein the hard mask comprises diamond, graphite, or hydrocarbon polymer.

4. The method of claim 1, wherein the pillar structure comprises a magnetic tunnel junction.

5. The method of claim 1, wherein the pillar structure comprises a spin-valve structure.

6. The method of claim 1, wherein the pillar structure comprises a phase-change memory structure.

7. The method of claim 1, wherein the step of utilizing the hard mask to pattern at least a portion of the pillar structure comprises reactive ion etching.

8. The method of claim 1, wherein the step of utilizing the hard mask to pattern at least a portion of the pillar structure comprises ion milling.

9. The method of claim 1, wherein the step of removing the hard mask comprises etching with a plasma comprising atomic oxygen or atomic hydrogen, or a combination thereof.

10. The method of claim 1, further comprising the step of trimming the hard mask for narrowing the hard mask without reducing the height of the hard mask and without narrowing a width of the hard mask cap and the pillar structure.

11. The method of claim 1, wherein the pillar structure has a width or diameter less than about 100 nanometers.

12. The method of claim 1, wherein the conductive material is planarized to the top surface of the upper dielectric layer.

13. A pillar structure that is contacted by a vertical contact in an integrated circuit, the pillar structure and vertical contact formed at least in part by the steps of:

sequentially depositing pillar structure material layers, a hard mask layer and a hard mask cap layer on a substrate;

patterning the hard mask cap and hard mask layers to form a hard mask cap and a hard mask on the pillar structure material layers, the hard mask comprising carbon;

utilizing the hard mask cap and the hard mask to pattern at least a portion of the pillar structure material layers to form a pillar structure;

depositing a liner on the hard mask cap, hard mask and pillar structure;

forming a lower dielectric layer in contact with a side portion of the liner;

depositing a stop layer on top of the lower dielectric layer and a portion of the liner disposed above the hard mask cap, hard mask and pillar structure;

forming an upper dielectric layer on top of the stop layer;

forming a trench in the upper dielectric layer down to the stop layer;

removing the stop layer and the liner and the hard mask ca selectively to exposed surfaces of the lower and upper dielectric layers and the hard mask to expose an upper surface of the hard mask;

removing the hard mask; and

depositing a conductive material into the trench and a region previously occupied by the hard mask to form the vertical contact and a conductive line.

14. The pillar structure that is contacted by a vertical contact in an integrated circuit of claim 13, wherein the pillar structure and vertical contact are formed at least in part by a further step of trimming the hard mask for narrowing the hard mask without reducing the height of the hard mask and without narrowing a width of the hard mask cap and the pillar structure.

15. An integrated circuit comprising a pillar structure that is contacted by a vertical contact, the pillar structure and the vertical contact formed at least in part by the steps of:

sequentially depositing pillar structure material layers, a hard mask layer and a hard mask cap layer on a substrate;

patterning the hard mask cap and hard mask layers to form a hard mask cap and a hard mask on the pillar structure material layers, the hard mask comprising carbon;

utilizing the hard mask cap and the hard mask to pattern at least a portion of the pillar structure material layers to form a pillar structure;

depositing a liner on the hard mask cap, hard mask and pillar structure;

forming a lower dielectric layer in contact with a side portion of the liner;

depositing a stop layer on top of the lower dielectric layer and a portion of the liner disposed above the hard mask cap, hard mask and pillar structure;

forming an upper dielectric layer on top of the stop layer;

forming a trench in the upper dielectric layer down to the stop layer;

removing the stop layer and the liner and the hard mask cap selectively to exposed surfaces of the lower and upper dielectric layers and the hard mask to expose an upper surface of the hard mask;

removing the hard mask; and

depositing a conductive material into the trench and a region previously occupied by the hard mask to form the vertical contact and a conductive line.

16. The integrated circuit comprising a pillar structure that is contacted by a vertical contact of claim 15, wherein the pillar structure and the vertical contact are formed at least in part by a further step of trimming the hard mask for narrowing the hard mask without reducing the height of the hard mask and without narrowing a width of the hard mask cap and the pillar structure.