Light emitting device having light extraction structure and method for manufacturing the same

• US 8,008,103 B2
• Filed: 12/14/2009
• Issued: 08/30/2011
• Est. Priority Date: 05/08/2006
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation), LG Innotek Company Limited (LG Corporation)
• Inventors: Jang, Jun Ho, Kim, Sun Kyung, Cho, Hyun Kyong
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US12/637,653
• Publication Number:
  US 20100093123A1
• Time in Patent Office: 624 Days
• Field of Search: 438/459, 438/977, 438/42, 438/46, 438/47, 257/95, 257/98, 257/E33.074, 257/E33.067, 257/E33.068
• US Class Current: 438/42
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.

Claims

1. A method for manufacturing a light emitting device, comprising:

growing a semiconductor structure having multi-layers over a substrate;

forming a first electrode over a first surface of the semiconductor structure;

providing a support layer on the first electrode;

removing the substrate from a second surface of the semiconductor structure;

forming a dielectric layer over the second surface of the semiconductor structure;

forming a plurality of holes in the dielectric layer;

forming a plurality of grooves in the semiconductor structure by using the dielectric layer as a mask, the grooves forming a rough surface through which light is extracted or a photonic crystal structure;

removing the dielectric layer; and

forming a second electrode over the second surface of the semiconductor structure.

2. The method according to claim 1, wherein growing the semiconductor structure comprises:

forming a first-type semiconductor layer over the substrate;

forming an active layer over the first-type semiconductor layer; and

forming a second-type semiconductor layer over the active layer.

3. The method according to claim 2, wherein the first-type is n-type and the second-type is p-type.

4. The method according to claim 2, wherein the grooves are formed with a depth corresponding to ⅓

or more of a thickness of the first-type semiconductor layer.

5. The method according to claim 1, wherein the dielectric layer comprises an oxide or a nitride.

6. The method according to claim 1, wherein the holes or the grooves are formed with a regular pattern.

7. The method according to claim 6, wherein the regular pattern comprises one of a square pattern, an oblique-line pattern, a concentric pattern, a polygonal pattern, a trapezoidal pattern, or a radial pattern.

8. The method according to claim 1, wherein forming the plurality of holes or forming the plurality of grooves is carried out by using a dry etching process.

9. The method according to claim 8, wherein the dry etching process is a reactive ion etching (RIE) process or an inductively-coupled plasma reactive ion etching (ICP-RIE) process.

10. The method according to claim 8, wherein the dry etching process is performed by using at least one of Ar, BCl₃, Cl₂, CF₄, and CHF₃.

11. The method according to claim 1, wherein forming the plurality of holes in the dielectric layer is performed by forming the holes in a region where the second electrode is not to be formed.

12. The method according to claim 11, wherein the second electrode is formed on the region.

13. The method according to claim 1, wherein the grooves are configured to enhance light extraction efficiency of the light emitting device.

14. The method according to claim 1, wherein each photonic crystal structure has a periodicity of 0.5 to 1.5 μ

m.

15. The method according to claim 14, wherein the groove has a diameter corresponding to about 0.3 to 0.6 times of the periodicity.

16. The method according to claim 1, wherein the first electrode comprises a reflective electrode.

17. The method according to claim 1, wherein forming the plurality of holes is carried out by using a pattern mask on the dielectric layer.

18. The method according to claim 17, wherein the pattern mask comprises a metal or a photoresist.

19. The method according to claim 1, wherein the second surface is a main light emitting surface of the light emitting device.

20. The method according to claim 1, wherein the grooves are irregularly distributed to form the rough surface.

21. The method according to claim 1, wherein providing the support layer comprises bonding a semiconductor substrate.

22. The method according to claim 21, wherein the semiconductor substrate comprises silicon, gallium arsenide, or germanium.

23. The method according to claim 1, wherein providing the support layer comprises plating a metal.

24. The method according to claim 23, wherein the metal comprises nickel or copper.

25. The method according to claim 1, further comprising forming a seed metal on the first electrode.

26. The method according to claim 1, wherein removing the substrate is performed by a laser lift-off process or an etching process.

27. The method according to claim 1, wherein the semiconductor structure comprises a GaN-based semiconductor.