Shallow source MOSFET

• US 8,008,151 B2
• Filed: 11/09/2007
• Issued: 08/30/2011
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Ho, Moses, Tai, Sung-Shan, Li, Tiesheng, Chang, Hong
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US11/983,769
• Publication Number:
  US 20080090357A1
• Time in Patent Office: 1,390 Days
• Field of Search: 438/259, 438/270, 438/589, 257/E21.655
• US Class Current: 438/259
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a hard mask on a substrate having a top substrate surface;

forming a plurality of trenches in the substrate, through the hard mask;

depositing gate material in the plurality of trenches, where the amount of gate material deposited in the plurality of trenches extends beyond the top substrate surface;

removing the hard mask to leave a plurality of gates that extend substantially above the top substrate surface;

forming a body in the substrate;

forming a plurality of source regions in the body, including a first source region adjacent to a first one of the plurality of gates and a second source region adjacent to a second one of the plurality of gates; and

forming a plurality of spacers to insulate at least some of the plurality of source regions from at least some of the plurality of gates;

disposing a conductor to form a thin conductive layer on at least a portion of the top substrate surface between the first one of the plurality of gates and the second one of the plurality of gates to connect the first source region and the second source region electrically, on at least a portion of the first source region, and on at least a portion of the second source region, wherein the thickness of the thin conductive layer is substantially less than height of the plurality of spacers.

2. A method of fabricating a semiconductor device as recited in claim 1, wherein the hard mask is a SiO₂ hard mask.

3. A method of fabricating a semiconductor device as recited in claim 1, wherein the plurality of trenches are formed to be mutually aligned with the hard mask.

4. A method of fabricating a semiconductor device as recited in claim 1, wherein forming the plurality of spacers includes disposing a dielectric layer on the substrate, and etching the dielectric layer without a mask.

5. A method of fabricating a semiconductor device as recited in claim 1, further comprising:

disposing a layer of dielectric material that covers at least the plurality of gates and at least a portion of the thin conductive layer; and

forming a first contact opening through the layer of dielectric material between the first one of the plurality of gates and the second one of the plurality of gates, and a second contact opening through the layer of dielectric material, above a third gate.

6. A method of fabricating a semiconductor device as recited in claim 5, wherein at least some of the plurality of spacers are used to provide precision alignment for forming the first contact opening and the second contact opening.

7. A method of fabricating a semiconductor device as recited in claim 5, wherein the first contact opening and the second contact opening are formed using a contact mask to pattern the dielectric material.

8. A method of fabricating a semiconductor device as recited in claim 5, wherein the first contact opening and the second contact opening are formed using an etch mask.

9. The method of claim 1, wherein the thin conductive layer is further disposed on top of at least some of the plurality of gates.

10. The method of claim 9, wherein one of the plurality of spacers separates the first source region and the first one of the plurality of gates.