Semiconductor device manufacturing method, semiconductor manufacturing apparatus and storage medium
First Claim
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1. A semiconductor device manufacturing method comprising:
- reducing or removing a natural oxide of copper on a surface of a lower layer conductive path exposed at a bottom of a recess formed in an interlayer insulating film of a surface of a substrate by supplying an organic acid to the substrate;
forming an oxygen supplying layer in the recess from organic acid;
forming a seed layer having a self-forming barrier metal along a wall surface of the recess on the substrate from which the natural oxide is reduced or removed;
after forming the oxygen supplying layer, burying, in the recess, copper forming an upper layer conductive path electrically connected to the lower layer conductive path via the seed layer; and
heating the substrate,wherein until the seed layer is formed after the natural oxide of copper is reduced or removed, a formation of the natural oxide of copper is suppressed in an atmosphere to which the substrate is exposed.
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Abstract
A seed layer is formed on a surface of an insulating film and along a recess of the insulating film, and after a copper wiring is buried in the recess, a barrier film is formed, and an excessive metal is removed from the wiring. On a surface of a copper lower layer conductive path exposed at the bottom of the recess, a natural oxide of the copper is reduced or removed. On a substrate from which the natural oxide is reduced or removed, the seed layer, composed of a self-forming barrier metal having oxidative tendency higher than that of copper or an alloy of such metal and copper, is formed. The substrate is heated after burying copper in the recess. Thus, a barrier layer is formed by oxidizing the self-forming barrier metal. An excessive portion of the self-forming barrier metal is deposited on a surface of the buried copper.
36 Citations
14 Claims
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1. A semiconductor device manufacturing method comprising:
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reducing or removing a natural oxide of copper on a surface of a lower layer conductive path exposed at a bottom of a recess formed in an interlayer insulating film of a surface of a substrate by supplying an organic acid to the substrate; forming an oxygen supplying layer in the recess from organic acid; forming a seed layer having a self-forming barrier metal along a wall surface of the recess on the substrate from which the natural oxide is reduced or removed; after forming the oxygen supplying layer, burying, in the recess, copper forming an upper layer conductive path electrically connected to the lower layer conductive path via the seed layer; and heating the substrate, wherein until the seed layer is formed after the natural oxide of copper is reduced or removed, a formation of the natural oxide of copper is suppressed in an atmosphere to which the substrate is exposed. - View Dependent Claims (2, 3, 7, 8, 9, 10, 11, 12, 13, 14)
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4. A semiconductor device manufacturing method comprising:
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reducing or removing a natural oxide of copper on a surface of a lower layer conductive path exposed at a bottom of a recess formed in an interlayer insulating film of a surface of a substrate by supplying an organic acid to the substrate; forming an oxygen supplying layer in the recess from organic acid; after forming the oxygen supplying layer, burying in the recess an alloy of copper and a self-forming barrier metal forming an upper layer conductive path electrically connected to the lower layer conductive path on the substrate from which the natural oxide is reduced or removed; and heating the substrate, wherein until the alloy is buried in the recess after the natural oxide of copper is reduced or removed, a formation of the natural oxide of copper is suppressed in an atmosphere to which the substrate is exposed. - View Dependent Claims (5, 6)
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Specification
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Current AssigneeTohoku University National Universities Corporation, Tokyo Electron Limited
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Original AssigneeTohoku University National Universities Corporation, Tokyo Electron Limited
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InventorsNeishi, Koji, Matsumoto, Kenji, Hosaka, Shigetoshi, Koike, Junichi
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Primary Examiner(s)Mulpuri; Savitri
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Application NumberUS12/627,602Publication NumberTime in Patent Office638 DaysField of Search438618-688, 257/E21.584US Class Current438/618CPC Class CodesH01L 21/28556 by chemical means, e.g. CVD...H01L 21/76844 Bottomless linersH01L 21/76855 After-treatment introducing...H01L 21/76873 for electroplatingH01L 21/76883 Post-treatment or after-tre...H01L 23/53238 Additional layers associate...H01L 23/53295 Stacked insulating layersH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
