Non-volatile memory cell with embedded antifuse

• US 8,008,700 B2
• Filed: 06/28/2007
• Issued: 08/30/2011
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kumar, Tanmay, Herner, S. Brad
• Primary Examiner(s): Bryant; Kiesha
• Assistant Examiner(s): WRIGHT, TUCKER J
• Application Number:
  US11/819,618
• Publication Number:
  US 20080017912A1
• Time in Patent Office: 1,524 Days
• Field of Search: 257313-314, 257/530, 365/63
• US Class Current: 257/314
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00

Abstract

A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion.

Claims

1. A nonvolatile memory device, comprising at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse dielectric layer separating the first diode portion from the second diode portion, wherein

the first diode portion, the antifuse and the second diode portion form a pillar having a substantially cylindrical shape;

the first diode portion and the second diode portion are adapted to form a diode when the antifuse dielectric layer is ruptured by a conductive link;

the diode comprises a doped polycrystalline silicon, germanium or silicon-germanium material p-i-n pillar diode in which the polycrystalline material comprises at least one of (a) plurality of grain boundaries (b) a degree of order;

the antifuse dielectric layer comprises a silicon oxide, silicon nitride, or metal oxide layer; and

when in use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias, wherein;

(a) at least some dopant atoms move away from at least some of the plurality of grain boundaries during switching from the first resistivity state to the second resistivity state, or (b) the degree of order increases during switching from the first resistivity state to the second resistivity state.

2. The device of claim 1, wherein:

the first diode portion comprises a p-type semiconductor region and the second diode portion comprises an n-type semiconductor region; and

the antifuse comprises an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region.

3. The device of claim 1, further comprising a not intentionally doped intrinsic semiconductor region located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region.

4. The device of claim 3, further comprising:

a first electrode located above a substrate and below the memory cell; and

second electrode located above the memory cell.

5. The device of claim 4, wherein the p-type semiconductor region is located below the antifuse dielectric layer and the n-type semiconductor region is located above the antifuse dielectric layer.

6. The device of claim 4, wherein the n-type semiconductor region is located below the antifuse dielectric layer and the p-type semiconductor region is located above the anti fuse dielectric layer.

7. The device of claim 4, wherein the intrinsic semiconductor region is located below the antifuse dielectric layer.

8. The device of claim 4, wherein the intrinsic semiconductor region is located above the antifuse dielectric layer.

9. The device of claim 4, wherein the antifuse dielectric layer comprises at least one hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride.

10. The device of claim 4, wherein:

the memory cell comprises a rewritable memory cell;

the antifuse dielectric layer is ruptured by a conductive link by an application of a forward bias between the first and the second electrodes to program the diode;

the programmed diode is adapted to be placed in a high resistivity, unprogrammed state by an application of a reverse bias to the diode having a value greater than a predetermined critical voltage value; and

the unprogrammed diode is adapted to be returned to the low resistivity, programmed state by an application of a forward bias to the diode.

11. The device of claim 1, wherein the device comprises a monolithic, three dimensional array of memory cells.

12. The device of claim 1, wherein the applied bias comprises a set pulse, and the first resistivity state has a higher resistivity than the second resistivity state.

13. The device of claim 12, wherein:

wherein the diode is configured to switch from the second resistivity state to a third resistivity state higher than the second resistivity state in response to an applied reset bias; and

at least some of the dopant atoms move crystal grains to at least some of the plurality of grain boundaries during switching from the second resistivity state to the third resistivity state.

14. The device of claim 12, wherein:

wherein the diode is configured to switch from the second resistivity state to a third resistivity state higher than the second resistivity state in response to an applied reset bias; and

the degree of order decreases during switching from the second resistivity state to the third resistivity state.

15. A nonvolatile memory device, comprising:

a substrate;

a first electrode located over the substrate;

a second electrode located over the first electrode; and

a plurality of memory cells located between the first electrode and the second electrode;

wherein each memory cell of the plurality of memory cells comprises;

a p-type semiconductor region;

an n-type semiconductor region;

an antifuse dielectric layer located between the p-type semiconductor region and the n-type semiconductor region;

a not intentionally doped intrinsic semiconductor region located adjacent to the antifuse dielectric layer between the p-type semiconductor region and the n-type semiconductor region; and

the p-type semiconductor region, the n-type semiconductor region, the antifuse dielectric layer and the intrinsic semiconductor region form a pillar having a substantially cylindrical shape; and

the diode comprises a doped polycrystalline silicon, germanium or silicon-germanium material, wherein the polycrystalline material comprises at least one of (a) a plurality of grain boundaries or (b) a degree of order;

where in use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias, wherein;

(a) at least some dopant atoms move away from at least some of the plurality of grain boundaries during switching from the first resistivity state to the second resistivity state, or (b) the degree of order increases during switching from the first resistivity state to the second resistivity state.

16. The device of claim 15, wherein:

the p-type semiconductor region and the n-type semiconductor region form a diode when the antifuse dielectric layer is ruptured by a conductive link;

the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode; and

the antifuse dielectric layer comprises a silicon oxide, silicon nitride, or a metal oxide layer.

17. The device of claim 16, wherein the p-type semiconductor region is located below the antifuse dielectric layer and the n-type semiconductor region is located above the antifuse dielectric layer.

18. The device of claim 16, wherein the n-type semiconductor region is located below the antifuse dielectric layer and the p-type semiconductor region is located above the antifuse dielectric layer.

19. The device of claim 16, wherein the intrinsic semiconductor region is located below the antifuse dielectric layer.

20. The device of claim 16, wherein the intrinsic semiconductor region is located above the antifuse dielectric layer.

21. The device of claim 15, wherein:

the memory cell comprises a rewritable memory cell;

the antifuse dielectric layer is ruptured by a conductive link by an application of a forward bias between the first and the second electrodes to program the diode;

the programmed diode is adapted to be placed in a high resistivity, unprogrammed state by an application of a reverse bias to the diode having a value greater than a predetermined critical voltage value; and

the unprogrammed diode is adapted to be returned to the low resistivity, programmed state by an application of a forward bias to the diode.