Insulated gate transistor incorporating diode

• US 8,008,711 B2
• Filed: 11/10/2006
• Issued: 08/30/2011
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): Skyles; Tifney L
• Application Number:
  US11/558,764
• Publication Number:
  US 20070069287A1
• Time in Patent Office: 1,754 Days
• Field of Search: 257/139, 257/328
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A p-type base layer shaped like a well is formed for each of IGBT cells, and a p⁺-type collector layer and an n⁺-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the p-type base layer. The p-type base layer of each of the IGBT cells includes a flat region including an emitter region and a bottom surface penetrated by a main trench, and first and second side diffusion regions between which the flat region is interposed. The first side diffusion region is situated just above the n⁺-type cathode layer and each of the bottom surfaces of the side diffusion regions forms a parabola-shaped smooth curve in longitudinal section. By replacing the p⁺-type collector layer with the n⁺-type cathode layer, it is possible to apply features of the above structure to a power MOSFET.

Claims

1. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first portion which includes a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a first main trench passing from said first main surface through the bottom surface of a first portion of said flat region of said first semiconductor layer, said first main trench comprising a bottom portion situated just below said first semiconductor layer in said semiconductor substrate;

an insulating film formed on said first main trench so that each of said bottom portion and a side surface of said first main trench is covered with said insulating film;

a control gate formed over said insulating film and filled into said first main trench;

a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said first portion of said flat region of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer;

a first main electrode formed on said top surface of said second semiconductor layer and said first side diffusion region of said first portion of said first semiconductor layer;

a third semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said third semiconductor layer, wherein

said first side surface of said second semiconductor layer is joined to said side surface of said first main trench,

said first side diffusion region in said first portion is situated just above said third semiconductor layer,

a bottom surface of said first side diffusion region is curved such that a depth of said first side diffusion region between said first main surface and the bottom surface of said first side diffusion region continuously decreases from a position of largest depth, where the first side diffusion region contacts the flat region, to a position within the first side diffusion region which is furthest away from the flat region, and

a bottom surface of said second side diffusion region is curved such that a depth of said second side diffusion region between said first main surface and a bottom surface of said second side diffusion region continuously decreases from a position of largest depth, where the second side diffusion region contacts the flat region, to a position within the second side diffusion region which is furthest away from the flat region;

said insulated gate transistor further comprises;

a second main trench which passes from said first main surface through a bottom surface of a second portion of said flat region of said first semiconductor layer, and comprises a bottom portion situated just below said first semiconductor layer in said semiconductor substrate; and

a first auxiliary trench passing from said first main surface through said curved bottom surface of said first side diffusion region and comprising a bottom portion situated below said first side diffusion region in said semiconductor substrate,

wherein said first and second main trenches are arranged in parallel to sandwich said flat region of said first semiconductor layer therebetween.

2. The insulated gate transistor according to claim 1, further comprising:

a second auxiliary trench passing from said first main surface through said curved bottom surface of said second side diffusion region and comprising a bottom portion situated below said second side diffusion region in said semiconductor substrate.

3. The insulated gate transistor according to claim 1, further comprising:

a fourth semiconductor layer of said second conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate,

wherein the third semiconductor layer and the fourth semiconductor layer are adjacent to each other and are in contact with the semiconductor substrate without any additional semiconductor layers between either of the third and fourth semiconductor layers and the semiconductor substrate.

4. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first portion which includes a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a first main trench passing from said first main surface through the bottom surface of a first portion of said flat region of said first semiconductor layer, said first main trench comprising a bottom portion situated just below said first semiconductor layer in said semiconductor substrate;

an insulating film formed on said first main trench so that each of said bottom portion and a side surface of said first main trench is covered with said insulating film;

a control gate formed over said insulating film and filled into said first main trench;

a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said first portion of said flat region of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer;

a first main electrode formed on said top surface of said second semiconductor layer and said first side diffusion region of said first portion of said first semiconductor layer;

a third semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said third semiconductor layer, wherein

said first side surface of said second semiconductor layer is joined to said side surface of said first main trench,

said first side diffusion region in said first portion is situated just above said third semiconductor layer,

a bottom surface of said first side diffusion region is curved such that a depth of said first side diffusion region between said first main surface and the bottom surface of said first side diffusion region continuously decreases from a position of largest depth, where the first side diffusion region contacts the flat region, to a position within the first side diffusion region which is furthest away from the flat region, and

a bottom surface of said second side diffusion region is curved such that a depth of said second side diffusion region between said first main surface and a bottom surface of said second side diffusion region continuously decreases from a position of largest depth, where the second side diffusion region contacts the flat region, to a position within the second side diffusion region which is furthest away from the flat region;

said insulated gate transistor further comprises;

a second main trench which passes from said first main surface through a bottom surface of a second portion of said flat region of said first semiconductor layer, and comprises a bottom portion situated just below said first semiconductor layer in said semiconductor substrate;

a first auxiliary trench passing from said first main surface through said curved bottom surface of said first side diffusion region and comprising a bottom portion situated below said first side diffusion region in said semiconductor substrate; and

a second auxiliary trench passing from said first main surface through said curved bottom surface of said second side diffusion region and comprising a bottom portion situated below said second side diffusion region in said semiconductor substrate.