Inverted-trench grounded-source FET structure with trenched source body short electrode

• US 8,008,716 B2
• Filed: 09/17/2006
• Issued: 08/30/2011
• Est. Priority Date: 09/17/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Hébert, François, Lui, Sik K
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): WRIGHT, TUCKER J
• Application Number:
  US11/522,669
• Publication Number:
  US 20080067584A1
• Time in Patent Office: 1,808 Days
• Field of Search: 257/330, 257/331, 257/332, 257/341, 257/E29.26, 257/E29.257
• US Class Current: 257/332
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Claims

1. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprises:

a vertical current conducting channel between said source and said drain disposed along a trenched gate padded by a gate oxide disposed on sidewalls of a trench opened in said semiconductor substrate;

a trenched source-body short structure comprises a conductive plug filled in a source-body contact trench wherein said conductive plug extending downwardly in said source-body contact trench from a top surface to a bottom surface of the source-body contact trench above the source disposed at the bottom of said semiconductor substrate with a body dopant region surrounding a bottom portion of said source-body contact trench for electrically shorting a body region surrounding said trenched gate in said substrate to said source disposed on said bottom of said substrate; and

said conductive plug in said body-source short structure further comprising a conductive Titanium silicide extending downwardly in said source-body contact trench from said top surface of said semiconductor substrate to said source region.

2. The iT-FET semiconductor device of claim 1 further comprising:

a termination region disposed on a peripheral area of said semiconductor substrate and said trenched source-body short structure is disposed in the termination region.

3. The iT-FET semiconductor device of claim 2 further comprising:

a drift region having a same conductivity type as said source region disposed near said top surface of said substrate surrounding an upper portion of said trenched gate and encompassing said drain; and

a link region having the same conductivity type as said source region disposed below said drift region and extending downwardly to said body region for linking said drift region and said body region for providing a source to body current channel.

4. The iT-FET semiconductor device of claim 3 wherein comprising:

said drift region is a N-drift region and is left unconnected for constituting a floating N-drift region and having substantially a source voltage whereby a die-sawing damage to said iT-FET device caused by grounding said N-drift region is reduced.

5. The iT-FET semiconductor device of claim 3 wherein comprising:

said body region is formed in an N-epitaxial layer in said semiconductor substrate as an implanted body region.

6. The iT-FET semiconductor device of claim 3 wherein comprising:

said source-body short structure constituting a conductive plug extending downwardly from a bottom surface of a buried conductor trench disposed in a termination area for on said semiconductor substrate for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate and further for shorting said source disposed on said bottom of said substrate to a source pad disposed on a top surface of said semiconductor substrate.

7. The iT-FET semiconductor device of claim 1 further comprising:

a region having a same conductivity type as said source region disposed below a bottom surface of said trenched gate functioning as a top portion of said source region surrounded by said body region doped with a body dopant having an opposite conductivity type than said source region.

8. The iT-FET semiconductor device of claim 1 wherein:

said trenched gate further comprising a thick spacer-oxide layer disposed on an upper portion of said sidewalls for insulating said trenched gate from said drain disposed near a top surface of said semiconductor substrate to further reduce a gate-drain coupling capacitance.

9. The iT-FET semiconductor device of claim 1 wherein:

said source further comprising a N+ doped substrate layer disposed on said bottom of said substrate.

10. The iT-FET semiconductor device of claim 9 wherein:

said drain further comprising a N+ doped region disposed immediately below a drain metal layer covering said top surface of said semiconductor substrate.

11. The iT-FET semiconductor device of claim 9 wherein:

said body region comprising a P doped region disposed in said substrate and surrounding a bottom portion of said trenched gate extending downwardly to said source.

12. The iT-FET semiconductor device of claim 9 wherein:

said bottom of said semiconductor substrate further comprising a N+ doped layer to function as a contact-enhancement layer for enhancing an electrical contact to said source region.

13. The iT-FET semiconductor device of claim 1 further comprising:

a termination area disposed near a peripheral area of said semiconductor substrate; and

a trenched gate runner extending from a central portion of said semiconductor to the peripheral area of said semiconductor substrate for electrically connecting a termination trenched gate to said trenched gate for electrically connecting the termination trenched gate to a gate metal disposed on top of said termination trenched gate in said termination area.

14. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprises a bottom source metal oxide semiconductor field effect transistor (MOSFET) device.

15. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprises:

a vertical current conducting channel between said source and said drain disposed along a trenched gate padded by a gate oxide disposed on sidewalls of a trench opened in said semiconductor substrate;

a trenched source-body short structure comprises a conductive plug filled in a source-body contact trench wherein said conductive plug extending downwardly in said source-body contact trench from a top surface to a bottom surface of the source-body contact trench above the source disposed at the bottom of said semiconductor substrate with a body dopant region surrounding a bottom portion of said source-body contact trench for electrically shorting a body region surrounding said trenched gate in said substrate to said source disposed on said bottom of said substrate; and

said conductive plug in said body-source short structure further comprising a conductive Cobalt silicide extending downwardly in said source-body contact trench from said top surface of said semiconductor substrate to said source region.

16. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprises:

a vertical current conducting channel between said source and said drain disposed along a trenched gate padded by a gate oxide disposed on sidewalls of a trench opened in said semiconductor substrate;

a trenched source-body short structure comprises a conductive plug filled in a source-body contact trench wherein said conductive plug extending downwardly in said source-body contact trench from a top surface to a bottom surface of the source-body contact trench above the source disposed at the bottom of said semiconductor substrate with a body dopant region surrounding a bottom portion of said source-body contact trench for electrically shorting a body region surrounding said trenched gate in said substrate to said source disposed on said bottom of said substrate; and

said conductive plug in said body-source short structure further comprising a conductive Tungsten silicide extending downwardly in said source-body contact trench from said top surface of said semiconductor substrate to said source region.