Transistor structure having a conductive layer formed contiguous in a single deposition

• US 8,008,720 B2
• Filed: 10/09/2008
• Issued: 08/30/2011
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Ahmed, Selim
• Application Number:
  US12/248,809
• Publication Number:
  US 20100090272A1
• Time in Patent Office: 1,055 Days
• Field of Search: 257/328, 257/349, 257/341, 257/E29.03, 257/E29.256, 257/E29.262, 257/E21.417, 257/E21.41, 257/329, 438/197, 438/268
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.

Claims

1. A transistor comprising:

a drain region of a first conductivity type;

a pedestal comprising at least a first dielectric layer, a second dielectric layer, and a third dielectric layer wherein the pedestal overlies at least a portion of the drain region and wherein the pedestal has a sidewall surface and a first major surface; and

a first conductive layer overlying the sidewall surface and the first major surface of the pedestal wherein a vertical portion of the first conductive layer adjacent to the sidewall surface of the pedestal comprises a gate of the transistor, wherein the first conductive layer is formed contiguous in a single deposition, and wherein a side wall of the first dielectric layer is etched to create an isotropic profile at a drain side of the gate.

2. The transistor of claim 1, further comprising:

a tub region of a second conductivity type wherein a portion of the tub region underlies the gate of the transistor and wherein the portion of the tub region underlying the gate of the transistor is a channel region of the transistor; and

a source region of the first conductivity type formed in the tub region.

3. The transistor of claim 2, wherein the tub region and the source region are electrically shorted together.

4. The transistor of claim 2, further comprising:

a second conductive layer overlying the first and second dielectric layers and underlying the third dielectric layer where the second conductive layer is a shield of the transistor; and

a fourth dielectric layer overlying the sidewall of the pedestal where the third dielectric layer isolates the second conductive layer from the first conductive layer.

5. The transistor of claim 4, wherein the second conductive layer is coupled to the source region.

6. The transistor of claim 4, further comprising:

a substrate of the first conductivity type underlying the drain region of the transistor; and

a first trench in the drain region of the transistor wherein a portion of the first trench underlies the pedestal, wherein the first trench has a sidewall surface and a major surface underlying a major surface of the drain region, and wherein the first trench includes a fifth dielectric layer overlying the sidewall surface and the major surface of the of the first trench.

7. The transistor of claim 5, further comprising:

a first doped region of the first conductivity type in proximity to the major surface of the drain region; and

a second doped region of the first conductivity type in proximity to the sidewall surface of the first trench.

8. The transistor of claim 6, wherein the second conductivity layer overlies the fourth dielectric layer along the sidewall of the first trench but not the major surface of the of the trench.

9. The transistor of claim 6, wherein the first trench is formed to a depth greater than a depth of the tub region.

10. The transistor of claim 6, wherein dopant below the major surface of the first trench is removed by etching.

11. The transistor of claim 6, further comprising a second trench underlying the first trench where the second trench extends through the drain region and into the substrate and wherein the second trench includes a sixth dielectric layer overlying a surface of the second trench.

12. A method of forming a transistor, the method comprising:

forming a drain region of a first conductivity type;

forming a pedestal overlying a portion of the drain region, the pedestal comprising a first dielectric layer, a second dielectric layer, a first conductive layer overlying the first and second dielectric layers, a third dielectric layer overlying the first conductive layer wherein the pedestal has a major surface and a sidewall;

capping the sidewall of the pedestal with a fourth dielectric layer to cover an exposed portion of the conductive layer; and

depositing a second conductive layer overlying the sidewall and major surface of the pedestal to respectively form a contiguous gate and gate interconnect in a single deposition.

13. The method of claim 12, further comprising:

forming a tub region of a second conductivity type adjacent to the drain region wherein a portion of the tub region underlies the gate of the transistor; and

forming a source region of the first conductivity type in the tub region.

14. The method of claim 13, further comprising:

etching a first trench in the drain region wherein the trench constrains lateral current flow of the transistor wherein the first trench has a sidewall and a major surface; and

implanting dopant of the first conductivity type through the sidewall of the first trench to form a doped region in the drain region in proximity to the sidewall of the first trench.

15. The method of claim 14, further comprising forming the first trench to a depth greater than a depth of the tub region.

16. The method of claim 15, further comprising:

implanting dopant of the first conductivity type in proximity to a major surface of the drain region;

etching the first major surface of the first trench to remove charge; and

forming a fifth dielectric layer overlying the sidewall and the first major surface of the first trench.

17. The method of claim 16, further comprising:

forming the first conductive layer overlying the fifth dielectric layer; and

etching a portion of the first conductive layer overlying the major surface of the first trench where the first conductive layer is a faraday shield of the transistor.

18. The method of claim 17, further comprising:

providing a substrate of the first conductivity type underlying the tub region, the drain region, and the first trench;

etching a second trench underlying the first trench wherein the second trench extends through the drain region and into the substrate; and

forming a sixth dielectric layer overlying a surface of the second trench.

19. A method of forming a transistor, comprising:

forming a drain region of a first conductivity type;

forming a pedestal overlying a portion of the drain region, the pedestal comprising at least a first dielectric layer and a second dielectric layer wherein the pedestal has a major surface and a sidewall;

depositing a first conductive layer overlying the sidewall and the major surface of the pedestal;

implanting dopant of a second conductivity type to form a tub region aligned to a vertical portion of the first conductive layer adjacent to the pedestal; and

depositing a second conductive layer on the first conductive layer wherein the combined thickness of the first and second conductive layers is a gate length of the transistor.

20. The method of claim 19, further comprising forming a source region in the tub region.

21. The method of claim 20, further comprising:

forming a second conductive layer overlying the second dielectric layer;

forming a third dielectric layer overlying the second conductive layer; and

forming a fourth dielectric layer overlying the sidewall of the pedestal to isolate the first conductive layer from the second conductive layer.

22. The method of claim 21, further comprising:

implanting a layer of dopant in proximity to a major surface of the drain region to support current flow from the channel region into the drain region; and

diffusing dopant with a thermal step such that the tub region underlies the first and second conductive layers adjacent to the sidewall of the pedestal to form a channel region of the transistor.

23. A transistor comprising:

a drain region of a first conductivity type;

a pedestal comprising a first dielectric layer, a second dielectric layer, a first conductive layer overlying the first and second dielectric layers, a third dielectric layer overlying the first conductive layer, and a fourth dielectric layer overlying a sidewall of the pedestal wherein the pedestal overlies a portion of the drain region and where the pedestal includes a first major surface; and

a second conductive layer overlying the sidewall surface and the first major surface of the pedestal wherein a vertical portion of the first conductive layer adjacent to the sidewall surface is a gate of the transistor and the second conductive layer is formed contiguous over the sidewall and major surface of the pedestal in a single deposition.

24. The transistor of claim 23, further comprising:

a tub region of a second conductivity type where a portion of the tub region underlies the gate and the portion underlying the gate is a channel region of the transistor; and

a source region of the first conductivity type formed in the tub region.

25. A transistor, comprising:

a drain region of a first conductivity type;

a pedestal comprising a stack of at least three horizontal dielectric layers and a stack of at least three or more vertical dielectric layers wherein the pedestal overlies a portion of the drain region and wherein the pedestal has a sidewall surface and a first major surface;

a first conductive layer overlying the sidewall surface and the first major surface of the pedestal

a tub region of a second conductivity type where a portion of the tub region underlies a vertical portion of the first conductive layer adjacent to the sidewall of the pedestal; and

a source region of the first conductivity type formed in the tub region.

26. The transistor of claim 25, further comprising a second conductive layer within the at least three horizontal dielectric layers of the pedestal.

27. The transistor of claim 26, wherein the at least three vertical dielectric layers form the sidewall of the pedestal.

28. The transistor of claim 27, wherein the tub region and the source region are electrically shorted together.