Semiconductor memory and method of manufacturing the same

• US 8,008,732 B2
• Filed: 09/20/2007
• Issued: 08/30/2011
• Est. Priority Date: 09/21/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio, Kiyotoshi, Masahiro, Arai, Fumitaka, Yamamoto, Akihito, Shirota, Riichiro
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Chen; Yu
• Application Number:
  US11/858,731
• Publication Number:
  US 20080073635A1
• Time in Patent Office: 1,440 Days
• Field of Search: 257/324, 257327-331, 257/326, 257/390, 257/E27.103, 365/185.17, 365/104, 365/182
• US Class Current: 257/390
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/021 : Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/028 : by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/801 : Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8413 : adapted for resistive heating
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Claims

1. A semiconductor memory, comprising:

a plurality of stripe-shaped semiconductor layers stacked on a substrate, patterned in self-alignment with each other and extending parallel to the substrate, each of the semiconductor layers having one end and other end parallel to the substrate, the one end being a source, the other end being a drain, the other ends of the semiconductor layers forming a stairs-shape;

a gate electrode formed only on side surfaces of the semiconductor layers and extending perpendicular to the substrate;

a plurality of cell transistors formed at intersections of the gate electrode and the side surfaces of the semiconductor layers and driven in the common gate electrode; and

a plurality of layer selecting transistors formed respectively on the other stairs-shaped ends of the semiconductor layers and selecting each of the semiconductor layers.

2. The memory according to claim 1, wherein the drains of the semiconductor layers are connected to a common interconnection.

3. The memory according to claim 1, wherein the sources of the semiconductor layers are connected to a common interconnection.

4. The memory according to claim 1, wherein the number of the semiconductor layers is 4 or more.

5. The memory according to claim 1, wherein the cell transistors are transistors of depletion type.

6. The memory according to claim 1, wherein the semiconductor layers are made of single-crystal silicon.

7. The memory according to claim 1, wherein the semiconductor layers are formed in a recess dug down from a top surface of the substrate, and a top most surface of the semiconductor layers is below the top surface of the substrate.

8. The memory according to claim 1, wherein a plurality of gate electrodes extending perpendicular to the substrate are formed only on side surfaces of the semiconductor layers and a plurality of cell transistors formed at intersections of the plurality of gate electrodes and one of the semiconductor layers form a NAND chain of a NAND flash memory.

9. The memory according to claim 1, wherein the semiconductor layers are equal in thickness.

10. The memory according to claim 1, wherein each of the semiconductor layers is formed on a corresponding insulating film.

11. The memory according to claim 1, wherein a plurality of stacked structures, each including the plurality of stripe-shaped semiconductor layers and extending in parallel with each other, are provided on the substrate, wherein a plurality of gate electrodes extending perpendicular to the substrate are filled between the plurality of stacked structures respectively, and the plurality of gate electrodes are connected with each other at a top most surface of the semiconductor layers.

12. The memory according to claim 1, wherein the plurality of layer selecting transistors are each a tri-gate type in which a gate electrode covers a top surface and the side surfaces of the other ends of the semiconductor layer.

13. A semiconductor memory, comprising:

a plurality of stripe-shaped semiconductor layers stacked on a substrate, patterned in self-alignment with each other and extending parallel to the substrate, each of the semiconductor layers having one end and other end parallel to the substrate, the one end being a source, the other end being a drain;

a gate electrode formed only on side surfaces of the semiconductor layers and extending perpendicular to the substrate;

a plurality of cell transistors formed at intersections of the gate electrode and the side surfaces of the semiconductor layers and driven by the common gate electrode; and

a plurality of layer selecting transistors selecting each of the semiconductor layers and being a tri-gate type, a gate electrode of each of the layer selecting transistors covering a top surface and side surfaces of a channel semiconductor.

14. The memory according to claim 13, wherein the number of the semiconductor layers is four or more.

15. The memory according to claim 13, wherein the cell transistors are transistors of depletion type.

16. The memory according to claim 13, wherein the cell transistors are made of single-crystal silicon.

17. The memory according to claim 13, wherein the semiconductor layers are formed in a recess dug down from a top surface of the substrate, and a top most surface of the semiconductor layers is below the top surface of the substrate.

18. The memory according to claim 13, wherein a plurality of gate electrodes extending perpendicular to the substrate are formed only on side surfaces of the semiconductor layers and a plurality of cell transistors formed at intersections of the plurality of gate electrodes and one of the semiconductor layers form a NAND chain of a NAND flash memory.

19. The memory according to claim 13, wherein the semiconductor layers are equal in thickness.

20. The memory according to claim 13, wherein a plurality of stacked structures, each including the plurality of stripe-shaped semiconductor layers and extending in parallel with each other, are provided on the substrate, wherein a plurality of gate electrodes extending perpendicular to the substrate are filled between the plurality of stacked structures respectively, and the plurality of gate electrodes are connected with each other at a top most surface of the semiconductor layers.