Semiconductor device with increased I/O leadframe
First Claim
1. A semiconductor package comprising:
- a generally planar die pad defining multiple peripheral edge segments;
a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad;
a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad;
a semiconductor die attached to the die pad and portions of the first leads, the semiconductor die being electrically connected to at least one of each of the first and second leads; and
a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of at least some of the second leads protrude from at least one of the side surfaces of the package body.
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Accused Products
Abstract
In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.
373 Citations
21 Claims
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1. A semiconductor package comprising:
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a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a semiconductor die attached to the die pad and portions of the first leads, the semiconductor die being electrically connected to at least one of each of the first and second leads; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of at least some of the second leads protrude from at least one of the side surfaces of the package body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor package comprising:
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a generally planar die pad; a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being disposed in spaced relation to the die pad; a plurality of second leads, at least some of which include a downset formed therein, the second leads being disposed in spaced relation to the die pad; a semiconductor die attached to the die pad and portions of the first leads, the semiconductor die being electrically connected to at least one of each of the first, and second leads; and a package body defining a opposed, generally planer top and, bottom surfaces, and multiple side surfaces, the package body at least partially encapsulating the first, and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with one of the top and bottom surfaces of the package body, and portions of at least some of the second leads protrude from at least one of the side surfaces of the package body. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor package comprising:
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a generally planar die pad defining opposed top and bottom surfaces and multiple peripheral edge segments; a plurality of first leads which each define a land and include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a semiconductor die attached to the die pad, the semiconductor die being electrically connected to at least one of each of the first and second leads; and a package body defining opposed top and bottom surfaces and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, the bottom surface of the die pad and the lands of the first leads are exposed in and substantially flush with one of the top and bottom surfaces of the package body, and portions of the second leads protrude from at least one of the side surfaces of the package body toward one of the ton and bottom surfaces thereof. - View Dependent Claims (20, 21)
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Specification