Post passivation interconnection structures
First Claim
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1. A circuit component connected to a wirebond, comprising:
- a silicon substrate;
a MOS device in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a contact pad over said silicon substrate;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises an insulating nitride;
a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point;
a coil on said first polymer layer;
an interconnect on said first polymer layer and on said contact point, wherein said interconnect is connected to said contact point through said second opening and to said wirebond, wherein said coil and said interconnect are provided by a patterned circuit layer on said first polymer layer and on said contact point, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises a glue layer, a seed layer on said glue layer, and an electroplated metal layer on said seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated metal layer; and
a second polymer layer over said first polymer layer and over said patterned circuit layer.
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Abstract
A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
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Citations
37 Claims
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1. A circuit component connected to a wirebond, comprising:
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a silicon substrate; a MOS device in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a contact pad over said silicon substrate; a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises an insulating nitride; a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point; a coil on said first polymer layer; an interconnect on said first polymer layer and on said contact point, wherein said interconnect is connected to said contact point through said second opening and to said wirebond, wherein said coil and said interconnect are provided by a patterned circuit layer on said first polymer layer and on said contact point, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises a glue layer, a seed layer on said glue layer, and an electroplated metal layer on said seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated metal layer; and a second polymer layer over said first polymer layer and over said patterned circuit layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 31)
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14. A circuit component comprising:
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a silicon substrate; a first polymer layer over said silicon substrate, wherein said first polymer layer has a thickness between 2 and 150 micrometers; a first metallization structure on said first polymer layer, wherein said metallization structure comprises a portion having a sheet resistance smaller than 7 milliohms per square, and wherein said first metallization structure comprises a coil on said first polymer layer, wherein said coil comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said electroplated gold layer is between 0.1 and 1 micrometer; and a second polymer layer over said first polymer layer and over said first metallization structure. - View Dependent Claims (15, 16, 17, 18, 19, 20, 32, 33, 34)
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21. A circuit component comprising:
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a semiconductor substrate; a first polymer layer over said semiconductor substrate, wherein said first polymer layer has a thickness between 2 and 150 micrometers; and a patterned circuit layer on said first polymer layer, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises at least a portion of an inductor and a contact point configured to be connected to a wirebond, wherein said patterned circuit layer comprises a titanium-containing layer, a gold seed layer having a thickness between 0.03 and 0.3 micrometers on said titanium-containing layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said electroplated gold layer is between 0.1 and 1 micrometer. - View Dependent Claims (22, 23, 24, 25, 26, 35, 36, 37)
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27. A circuit component comprising:
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a silicon substrate; a transistor in and on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said metallization structure, over said dielectric layer and over said silicon substrate, wherein an opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said opening, wherein said passivation layer comprises an insulating nitride; a patterned circuit layer over said passivation layer, on said first contact point and on a sidewall of said opening, wherein said patterned circuit layer contacts said passivation layer at said sidewall, wherein said patterned circuit layer is connected to said first contact point through said opening, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises at least a portion of an inductor and a second contact point configured to be connected to a metal bump, wherein said patterned circuit layer comprises a glue layer, a copper-containing seed layer on said glue layer, and an electroplated copper layer having a thickness between 3 and 20 micrometers on said copper-containing seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated copper layer; and a first polymer layer over said patterned circuit layer and over said passivation layer. - View Dependent Claims (28, 29, 30)
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Specification