Post passivation interconnection structures

• US 8,008,775 B2
• Filed: 12/20/2004
• Issued: 08/30/2011
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chien-Kang, Chou, Chiu-Ming, Lin, Mou-Shiung
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US11/017,169
• Publication Number:
  US 20060049525A1
• Time in Patent Office: 2,444 Days
• Field of Search: 257758-764, 257/781
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A circuit component connected to a wirebond, comprising:

a silicon substrate;

a MOS device in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a contact pad over said silicon substrate;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises an insulating nitride;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point;

a coil on said first polymer layer;

an interconnect on said first polymer layer and on said contact point, wherein said interconnect is connected to said contact point through said second opening and to said wirebond, wherein said coil and said interconnect are provided by a patterned circuit layer on said first polymer layer and on said contact point, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises a glue layer, a seed layer on said glue layer, and an electroplated metal layer on said seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated metal layer; and

a second polymer layer over said first polymer layer and over said patterned circuit layer.

2. The circuit component of claim 1, wherein said electroplated metal layer comprises an electroplated gold layer having a thickness between 1 and 20 micrometers.

3. The circuit component of claim 1, wherein said patterned circuit layer further comprises a nickel layer having a thickness between 0.1 and 3 micrometers on said electroplated metal layer.

4. The circuit component of claim 1, wherein said electroplated metal layer comprises an electroplated copper layer having a thickness between 3 and 20 micrometers.

5. The circuit component of claim 1, wherein said seed layer comprises a gold layer.

6. The circuit component of claim 1, wherein said seed layer comprises a copper layer.

7. The circuit component of claim 1, wherein said insulating nitride is the topmost insulating nitride of said circuit component.

8. The circuit component of claim 1, wherein said passivation layer further comprises an oxide.

9. The circuit component of claim 1, wherein said glue layer comprises a titanium-containing layer having a thickness between 0.02 and 0.2 micrometers.

10. The circuit component of claim 1, wherein said undercut is between 0.1 and 1 micrometer.

11. The circuit component of claim 1, wherein said first polymer layer comprises benzocyclobutene.

12. The circuit component of claim 1, wherein said first polymer layer comprises polyimide.

13. The circuit component of claim 1, wherein said glue/barrier layer comprises a titanium-tungsten alloy.

31. The circuit component of claim 1, wherein said second polymer layer is directly on said patterned circuit layer.

14. A circuit component comprising:

a silicon substrate;

a first polymer layer over said silicon substrate, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a first metallization structure on said first polymer layer, wherein said metallization structure comprises a portion having a sheet resistance smaller than 7 milliohms per square, and wherein said first metallization structure comprises a coil on said first polymer layer, wherein said coil comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said electroplated gold layer is between 0.1 and 1 micrometer; and

a second polymer layer over said first polymer layer and over said first metallization structure.

15. The circuit component of claim 14, wherein said first polymer layer comprises polyimide.

16. The circuit component of claim 14, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

17. The circuit component of claim 14, wherein said titanium-containing layer has a thickness between 0.05 and 0.5 micrometers.

18. The circuit component of claim 14, wherein said gold seed layer has a thickness between 0.03 and 0.3 micrometers.

19. The circuit component of claim 14 further comprising a separating layer between said first polymer layer and said silicon substrate, wherein said separating layer comprises a nitride.

20. The circuit component of claim 14, wherein said first polymer layer comprises benzocyclobutene.

32. The circuit component of claim 14 further comprising a second metallization structure between said silicon substrate and said first polymer layer, wherein said second metallization structure comprises aluminum.

33. The circuit component of claim 14 further comprising a second metallization structure between said silicon substrate and said first polymer layer, wherein said second metallization structure comprises damascene copper.

34. The circuit component of claim 14 further comprising a second metallization structure between said silicon substrate and said first polymer layer, wherein said second metallization structure comprises gold.

21. A circuit component comprising:

a semiconductor substrate;

a first polymer layer over said semiconductor substrate, wherein said first polymer layer has a thickness between 2 and 150 micrometers; and

a patterned circuit layer on said first polymer layer, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises at least a portion of an inductor and a contact point configured to be connected to a wirebond, wherein said patterned circuit layer comprises a titanium-containing layer, a gold seed layer having a thickness between 0.03 and 0.3 micrometers on said titanium-containing layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said electroplated gold layer is between 0.1 and 1 micrometer.

22. The circuit component of claim 21, wherein said first polymer layer comprises polyimide.

23. The circuit component of claim 21, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

24. The circuit component of claim 21, wherein said titanium-containing layer has a thickness between 0.05 and 0.5 micrometers.

25. The circuit component of claim 21 further comprising a second polymer layer en over said patterned circuit layer and over said first polymer layer.

26. The circuit component of claim 21 further comprising a nitride a separating layer between said first polymer layer and said semiconductor substrate, wherein said separating layer comprises a nitride.

35. The circuit component of claim 21 further comprising a metallization structure between said semiconductor substrate and said first polymer layer, wherein said metallization structure comprises aluminum.

36. The circuit component of claim 21 further comprising a metallization structure between said semiconductor substrate and said first polymer layer, wherein said metallization structure comprises damascene copper.

37. The circuit component of claim 21 further comprising a metallization structure between said semiconductor substrate and said first polymer layer, wherein said metallization structure comprises gold.

27. A circuit component comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, over said dielectric layer and over said silicon substrate, wherein an opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said opening, wherein said passivation layer comprises an insulating nitride;

a patterned circuit layer over said passivation layer, on said first contact point and on a sidewall of said opening, wherein said patterned circuit layer contacts said passivation layer at said sidewall, wherein said patterned circuit layer is connected to said first contact point through said opening, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises at least a portion of an inductor and a second contact point configured to be connected to a metal bump, wherein said patterned circuit layer comprises a glue layer, a copper-containing seed layer on said glue layer, and an electroplated copper layer having a thickness between 3 and 20 micrometers on said copper-containing seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated copper layer; and

a first polymer layer over said patterned circuit layer and over said passivation layer.

28. The circuit component of claim 27 further comprising a second polymer layer on said passivation layer, wherein said patterned circuit layer is further on said second polymer layer.

29. The circuit component of claim 27, wherein said glue layer comprises a titanium-containing layer.

30. The circuit component of claim 27, wherein said first polymer layer is directly on said patterned circuit layer.