Method and system for testing P2 stiffness of a magnetoresistance transducer at the wafer level

• US 8,008,912 B1
• Filed: 12/16/2008
• Issued: 08/30/2011
• Est. Priority Date: 12/16/2008
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital (Fremont) LLC (Western Digital Corporation)
• Inventors: Shang, Changhe
• Primary Examiner(s): Tang; Minh N
• Application Number:
  US12/336,218
• Time in Patent Office: 987 Days
• Field of Search: None
• US Class Current: 324/210
• CPC Class Codes: G01R 33/098 comprising tunnel junctions, e.g. tunnel magnetoresistance sensors

Abstract

A method of testing P2 stiffness of a magnetoresistance (MR) sensor stack including a P2 pinned layer is provided. The method comprises the step of applying an external magnetic field to the MR sensor stack. The external magnetic field is oriented substantially perpendicular to a magnetic field of the P2 pinned layer. The method further comprises varying an amplitude of the external magnetic field, measuring a change in a resistance of the MR sensor stack in response to the varying amplitude of the external magnetic field, and calculating the P2 stiffness based on the measured change in resistance.

Claims

1. A method of testing P2 stiffness of a magnetoresistance MR sensor stack including a P2 pinned layer, comprising the steps of:

applying an external magnetic field to the MR sensor stack, the external magnetic field oriented substantially perpendicular to a magnetic field of the P2 pinned layer;

varying an amplitude of the external magnetic field;

measuring a change in a resistance of the MR sensor stack in response to the varying amplitude of the external magnetic field; and

calculating the P2 stiffness based on the measured change in resistance.

2. The method according to claim 1, wherein the MR sensor stack comprises:

a free layer,

a barrier layer,

a synthetic antiferromagnetic layer including a P1 pinning layer, the P2 pinned layer and a spacer layer separating the P1 pinning layer and the P2 pinned layer,

an antiferromagnetic layer, and

a seed layer.

3. The method according to claim 2, wherein measuring the change in the resistance comprises measuring a change in resistance of a circuit path passing through the free layer, the barrier layer, the synthetic antiferromagnetic layer, the antiferromagnetic layer and the seed layer.

4. The method according to claim 1, wherein the external magnetic field is oriented substantially parallel to a magnetic field of a hard bias layer disposed adjacent to the MR sensor stack.

5. The method according to claim 1, wherein the amplitude of the external magnetic field is varied between about −

50% and 50% of a coercivity of a hard bias layer adjacent to the MR sensor stack.

6. The method according to claim 1, wherein the amplitude of the external magnetic field is varied between about −

1000 oersted and 1000 oersted.

7. The method according to claim 1, wherein measuring the change in the resistance of the MR sensor stack comprises measuring a change in the conductance of the MR sensor stack.

8. The method according to claim 1, wherein calculating the P2 stiffness comprises solving for H_P2S, where:

9. The method according to claim 8, wherein the MR sensor stack has a track width and a stripe height configured such that R_l and R_h are within a predetermined measurable range.

10. The method according to claim 1, wherein the MR sensor stack is a test structure with a track width of about 0.4 μ

m and a stripe height of about 2 μ

m.

11. The method according to claim 10, wherein the test structure includes two or more contact points for measuring the change in the resistance of the MR sensor stack.

12. The method according to claim 10, wherein the test structure is disposed in a test region of a wafer in which are also disposed one or more MR heads.

13. The method according to claim 1, wherein the P2 stiffness of the MR sensor stack is tested following the deposition of contact points on a wafer including the MR sensor stack.

14. The method according to claim 1, wherein the P2 stiffness of the MR sensor stack is tested after a wafer including the MR sensor stack has been sliced into one or more bars.

15. The method according to claim 1, wherein the MR sensor stack is a tunneling magnetoresistance (TMR) sensor stack.