Inverting zipper repeater circuit

• US 8,008,957 B2
• Filed: 12/01/2009
• Issued: 08/30/2011
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: Robert Paul Masleid
• Original Assignee: Robert Paul Masleid
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): Hiltunen; Thomas J
• Application Number:
  US12/628,715
• Publication Number:
  US 20100073055A1
• Time in Patent Office: 637 Days
• Field of Search: None
• US Class Current: 327/170
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 5/12 by steepening leading or trailing edges

Abstract

Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Claims

1. A method comprising:

delaying an input signal by using a first delay chain of inverters;

in response to a rising edge of the input signal, controlling an output to provide a first low logic level before a falling edge of the input signal;

in response to the falling edge of the input signal, controlling the output to provide a second logical level before the rising edge of the input signal; and

maintaining logic level of the output between the rising edge and the falling edge of the input signal by using a second delay chain of inverters, providing an output signal to the output, wherein the output signal of the second delay chain of inverters is excluded from an input of the first delay chain of inverters.

2. The method of claim 1, wherein the second logical level is a high logic level.

3. A method comprising:

delaying an input signal by using a first delay chain of inverters;

in response to a rising edge of the input signal, activating and deactivating a first circuit element before a falling edge of the input signal to provide an output falling edge signal at an output terminal;

in response to the falling edge of the input signal, activating and deactivating a second circuit element before the rising edge of the input signal to provide an output rising edge signal at the output terminal;

between the rising edge and the falling edge, holding a state of the output terminal by using a second delay chain of inverters, coupled to the output terminal wherein the first delay chain of inverters shares an inverter with the second delay chain of inverters; and

wherein the input of the first delay chain of inverters is excluded from the output terminal.

4. The method of claim 3, wherein the first circuit element comprises a first output transistor.

5. The method of claim 3, wherein the second circuit element comprises a second output transistor.

6. The method of claim 3, wherein the activating and deactivating the first circuit element comprises:

using a plurality of first transistors sized to respond to the rising edge faster than the falling edge.

7. The method of claim 3, wherein the activating and deactivating the second circuit element comprises:

using a plurality of second transistors sized to respond to the falling edge faster than the rising edge.

8. The method of claim 3, wherein the holding comprises:

using inverters that include differently sized transistors.

9. A method comprising:

delaying an input signal by using a first delay chain of inverters;

in response to a rising edge of the input signal, activating and deactivating a first circuit element before a falling edge of the input signal to provide an output falling edge signal at an output terminal;

in response to the falling edge of the input signal, activating and deactivating a second circuit element before the rising edge of the input signal to provide an output rising edge signal at the output terminal;

between the rising edge and the falling edge, maintaining a state of the output terminal by using a second delay chain of inverters, coupled to the output terminal wherein the first delay chain of inverters shares an inverter with the second delay chain of inverters; and

wherein the input of the first delay chain of inverters is excluded from the output terminal.

10. The method of claim 9, wherein the first circuit element comprises a first output transistor.

11. The method of claim 9, wherein the second circuit element comprises a second output transistor.

12. The method of claim 9, wherein the maintaining comprises:

using inverters that include differently sized transistors.

13. The method of claim 9, wherein the activating and deactivating the first circuit element comprises:

using a plurality of first transistors sized to respond to the rising edge faster than the falling edge.

14. The method of claim 9, wherein the activating and deactivating the second circuit element comprises:

using a plurality of second transistors sized to respond to the falling edge faster than the rising edge.