Method and apparatus for generating an analog signal having a pre-determined pattern

• US 8,009,073 B2
• Filed: 01/18/2010
• Issued: 08/30/2011
• Est. Priority Date: 05/23/2000
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Roo, Pierte
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/689,066
• Publication Number:
  US 20100127909A1
• Time in Patent Office: 589 Days
• Field of Search: 327/100, 327/103, 327/108, 327/126, 327/129, 327/131, 327132-136, 341/143, 341/144, 341/147, 375/295, 375/296
• US Class Current: 341/144
• CPC Class Codes: H03M 1/661 Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03834 using pulse shaping

Abstract

A circuit configured to generate an analog signal having a pre-determined pattern. The circuit includes a plurality of digital-to-analog converters. Each of the plurality of digital-to-analog converters includes a plurality of current sources configured to generate a plurality of square waveforms and a summer configured to sum the plurality of square waveforms to generate the analog signal having the pre-determined pattern. Each square waveform is delayed by a pre-determined amount delay relative to another square waveform of the plurality of square waveforms. The pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal. The pre-determined amount of delay is non-uniform throughout the circuit.

Claims

1. A circuit configured to generate an analog signal having a pre-determined pattern, the circuit comprising:

a plurality of digital-to-analog converters, wherein each of the plurality of digital-to-analog converters includes

a plurality of current sources configured to generate a plurality of square waveforms, wherein each square waveform is delayed by a pre-determined amount delay relative to another square waveform of the plurality of square waveforms,

a summer configured to sum the plurality of square waveforms to generate the analog signal having the pre-determined pattern,

wherein i) the pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal, and ii) the pre-determined amount of delay is non-uniform throughout the circuit.

2. The circuit of claim 1, wherein the pre-determined amount of delay is controlled by a delay-locked loop.

3. The circuit of claim 1, wherein the pre-determined amount of delay is controlled by a clock that is external to the circuit.

4. The circuit of claim 1, wherein the plurality of square waveforms are equal in magnitude and form.

5. The circuit of claim 1, wherein each of the plurality of current sources comprises a transistor-pair.

6. The circuit of claim 1, wherein each of the plurality of current sources comprises a differential transistor-pair.

7. The circuit of claim 1, wherein each of the plurality of current sources is operable to be turned off or on.

8. A transceiver comprising:

a plurality of circuits as recited in claim 1, wherein each circuit is configured to respectively (i) receive a digital input signal and (ii) generate a corresponding analog output signal; and

a plurality of low pass filters respectively in communication with the plurality of circuits, wherein each of the plurality of low pass filters is configured to respectively filter a corresponding analog output signal; and

an operational amplifier in communication with an output of each of the plurality of low pass filters.

9. The transceiver of claim 8, wherein the transceiver comprises an Ethernet transceiver.

10. The transceiver of claim 8, wherein the digital input signal received the by each of the plurality of circuits is a signal associated with a multi-level input signal.

11. A method of operating a circuit for generating an analog signal having a pre-determined pattern, the method comprising:

generating a plurality of square waveforms, wherein each square waveform is delayed by a pre-determined of delay amount relative to another square waveform of the plurality of square waveforms,

summing the plurality of square waveforms to generate the analog signal having the pre-determined pattern,

wherein i) the pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal, and ii) the pre-determined amount of delay is non-uniform throughout the circuit.

12. The method of claim 11, further comprising using a delay-locked loop to control the pre-determined amount of delay.

13. The method of claim 11, further comprising using a clock to control the pre-determined amount of delay.

14. The method of claim 11, wherein the plurality of square waveforms are equal in magnitude and form.