Pixel sensor cell with frame storage capability
First Claim
1. A semiconductor structure for a complementary metal oxide semiconductor (CMOS) image sensor pixel, said semiconductor structure comprising:
- a photosensitive diode structure;
a first transistor including a diffusion region and a first channel, wherein said diffusion region is a source region of said first transistor and is of integral construction with a terminal of said photosensitive diode structure;
a second transistor including a second channel located in proximity to said first channel, wherein said second channel is electrically coupled to said first channel to enable formation of a merged channel including said first channel and said second channel;
a plurality of frame transfer transistors including a plurality of frame transfer channels and configured to store a plurality of frames therein, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each of said plurality of frame transfer channels is located in proximity with another of said plurality of frame transfer channels to enable formation of a merged channel including two neighboring frame transistor channels; and
a set of four metal lines and a set of metal vias, wherein each of said set of four metal lines connects gate electrodes of every fourth frame transfer transistor among said plurality of frame transfer transistors through a subset of said metal vias, and wherein each of said four metal lines connects a different subset of said plurality of frame transfer transistors.
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Accused Products
Abstract
A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.
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Citations
17 Claims
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1. A semiconductor structure for a complementary metal oxide semiconductor (CMOS) image sensor pixel, said semiconductor structure comprising:
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a photosensitive diode structure; a first transistor including a diffusion region and a first channel, wherein said diffusion region is a source region of said first transistor and is of integral construction with a terminal of said photosensitive diode structure; a second transistor including a second channel located in proximity to said first channel, wherein said second channel is electrically coupled to said first channel to enable formation of a merged channel including said first channel and said second channel; a plurality of frame transfer transistors including a plurality of frame transfer channels and configured to store a plurality of frames therein, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each of said plurality of frame transfer channels is located in proximity with another of said plurality of frame transfer channels to enable formation of a merged channel including two neighboring frame transistor channels; and a set of four metal lines and a set of metal vias, wherein each of said set of four metal lines connects gate electrodes of every fourth frame transfer transistor among said plurality of frame transfer transistors through a subset of said metal vias, and wherein each of said four metal lines connects a different subset of said plurality of frame transfer transistors. - View Dependent Claims (2, 3, 4)
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5. A semiconductor structure for a complementary metal oxide semiconductor (CMOS) image sensor pixel, said semiconductor structure comprising:
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photosensitive diode structure; a first transistor including a diffusion region and a first channel, wherein said diffusion region is a source region of said first transistor and is of integral construction with a terminal of said photosensitive diode structure; a second transistor including a second channel located in proximity to said first channel, wherein said second channel is electrically coupled to said first channel to enable formation of a merged channel including said first channel and said second channel; a plurality of frame transfer transistors including a plurality of frame transfer channels and configured to store a plurality of frames therein, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each of said plurality of frame transfer channels is located in proximity with another of said plurality of frame transfer channels to enable formation of a merged channel including two neighboring frame transistor channels; and a set of three metal lines and a set of metal vias, wherein each of said set of three metal lines connects gate electrodes of every third frame transfer transistor among said plurality of frame transfer transistors through a subset of said metal vias, and wherein each of said three metal lines connects a different subset of said plurality of frame transfer transistors.
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6. A semiconductor circuit for a complementary metal oxide semiconductor (CMOS) image sensor pixel, said semiconductor circuit comprising:
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a photosensitive diode; a first transistor having a first channel, wherein a source of said first transistor is a terminal of said photosensitive diode; a second transistor having a second channel which is configured to enable formation of a merged channel including said first channel and said second channel; and a plurality of frame transfer transistors including a plurality of frame transfer channels and configured to store a plurality of frames therein, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each neighboring pair of said plurality of frame transfer channels is configured to enable formation of a merged channel including two neighboring frame transistor channels, wherein gates of every third frame transfer transistor among said plurality of frame transfer transistors are electrically shorted, and wherein gates of adjoining frame transfer transistors are electrically disconnected. - View Dependent Claims (7, 8, 9)
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10. A semiconductor circuit for a complementary metal oxide semiconductor (CMOS) image sensor pixel, said semiconductor circuit comprising:
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a photosensitive diode; a first transistor having a first channel, wherein a source of said first transistor is a terminal of said photosensitive diode; a second transistor having a second channel which is configured to enable formation of a merged channel including said first channel and said second channel; and a plurality of frame transfer transistors including a plurality of frame transfer channels and configured to store a plurality of frames therein, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each neighboring pair of said plurality of frame transfer channels is configured to enable formation of a merged channel including two neighboring frame transistor channels., wherein gates of every fourth frame transfer transistor among said plurality of frame transfer transistors are electrically shorted, and wherein gates of adjoining frame transfer transistors are electrically disconnected.
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11. A machine readable non-transitory storage medium embodying a design structure for designing, manufacturing, or testing a design for a complementary metal oxide semiconductor (CMOS) image sensor pixel configured to store a plurality of frames in a plurality of frame transfer transistors, said design structure comprising:
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a first data representing a photosensitive diode; a second data representing a first transistor in direct serial connection with said photosensitive diode, wherein said first transistor having a first channel, and wherein a source of said first transistor is a terminal of said photosensitive diode; a third data representing a second transistor in direct serial connection with said first transistor, wherein said second transistor having a second channel configured to enable formation of a merged channel including said first channel and said second channel; a fourth data representing a plurality of frame transfer transistors serially connected thereamongst and configured to store a plurality of frames therein and in direct serial connection with said second transistor; and a fifth data representing an electrical connection between gate electrodes of every fourth frame transfer transistor among said plurality of frame transfer transistors, wherein gates of adjoining frame transfer transistors are electrically disconnected. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A machine readable non-transitory storage medium embodying a design structure for designing, manufacturing, or testing a design for a complementary metal oxide semiconductor (CMOS) image sensor pixel configured to store a plurality of frames in a plurality of frame transfer transistors, said design structure comprising:
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a first data representing a photosensitive diode; a second data representing a first transistor in direct serial connection with said photosensitive diode, wherein said first transistor having a first channel, and wherein a source of said first transistor is a terminal of said photosensitive diode; a third data representing a second transistor in direct serial connection with said first transistor, wherein said second transistor having a second channel configured to enable formation of a merged channel including said first channel and said second channel; a fourth data representing a plurality of frame transfer transistors serially connected thereamongst and configured to store a plurality of frames therein and in direct serial connection with said second transistor; and a fifth data representing an electrical connection between gate electrodes of every third frame transfer transistor among said plurality of frame transfer transistors, wherein gates of adjoining frame transfer transistors are electrically disconnected.
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Specification