Semiconductor wafer analysis system
First Claim
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1. A semiconductor wafer analysis system comprising:
- a tester adapted to output test results responsive to a test of presence and type of defects on semiconductor wafers manufactured by at least one manufacturing facility;
a wafer map generation module adapted to generate wafer maps based on the test results from the tester; and
a wafer analysis module including a data generation module and an operation module, the data generation module adapted to divide each wafer map into a plurality of defect analysis regions and to generate feature vectors having defect values, which representing the semiconductor wafers at least one defect type occurring in each defect analysis region, as a plurality of component values, and the operation module adapted to statistically analyze the feature vectors so as to assist in the determination of a defective one or ore of the manufacturing facilities.
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Abstract
A semiconductor wafer analysis system is provided. In an embodiment, the semiconductor wafer analysis system includes a tester to test semiconductor wafers manufactured by at least one manufacturing facility, a wafer map generation module to generate wafer maps on the basis of the test results from the tester, and a wafer analysis module. The wafer analysis module may include a data generation module that divides each wafer map into a plurality of defect analysis regions and generates feature vectors representing the semiconductor wafers, and an operation module that statistically analyzes the feature vectors.
14 Citations
20 Claims
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1. A semiconductor wafer analysis system comprising:
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a tester adapted to output test results responsive to a test of presence and type of defects on semiconductor wafers manufactured by at least one manufacturing facility; a wafer map generation module adapted to generate wafer maps based on the test results from the tester; and a wafer analysis module including a data generation module and an operation module, the data generation module adapted to divide each wafer map into a plurality of defect analysis regions and to generate feature vectors having defect values, which representing the semiconductor wafers at least one defect type occurring in each defect analysis region, as a plurality of component values, and the operation module adapted to statistically analyze the feature vectors so as to assist in the determination of a defective one or ore of the manufacturing facilities. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor wafer analysis system comprising:
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a tester to test semiconductor wafers manufactured by at least one manufacturing facility; a wafer map generation module to generate wafer maps based on test results from the tester; and a wafer analysis module that includes a data generation module and an operation module, wherein the data generation module is adapted to divide each wafer map into a plurality of defect analysis regions and to generates feature vectors representing the semiconductor wafers, and the operation module is adapted to classify the feature vectors into clusters based on defect type by k-means clustering, and to determine whether a specific kind of defect occurs in each manufacturing facility by a chi-square analysis method. - View Dependent Claims (11, 12, 13, 14)
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15. A semiconductor wafer analysis method, comprising:
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testing semiconductor wafers manufactured by at least one manufacturing facility; generating wafer maps based on the testing; dividing each wafer map into a plurality of defect analysis regions; generating feature vectors having defect values, which represent at least one defect type occurring in each defect analysis region, as a plurality of component values, wherein the wafer maps visually display the at least one defect type; and statistically analyzing the feature vectors. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification