Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices
First Claim
1. A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:
- a plurality of parallel driver slices each comprising a plurality of cascaded digital logic driver stages for receiving and sending binary-valued logic signals, wherein all of said slices have common output nodes at each stage, whereby a drive current at each particular stage is generated as the sum of unequal individual drive currents of each slice at each particular stage; and
a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level.
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Abstract
A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
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Citations
18 Claims
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1. A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:
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a plurality of parallel driver slices each comprising a plurality of cascaded digital logic driver stages for receiving and sending binary-valued logic signals, wherein all of said slices have common output nodes at each stage, whereby a drive current at each particular stage is generated as the sum of unequal individual drive currents of each slice at each particular stage; and a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An interface including:
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a transmission circuit for transmitting a binary-valued digital logic signal to one or more interface conductors, comprising an output driver having a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein all of said slices have common output nodes at each stage, whereby a drive current at each particular stage is generated as the sum of unequal individual drive currents of each slice at each particular stage and a control logic for selectively enabling said parallel driver slices in response to one or more control signals, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level; and an interface quality measurement circuit for providing said one or more control signals in response to a determination of quality of signals on said interface conductors. - View Dependent Claims (10, 11, 12)
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13. A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:
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a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein all of said slices have common output nodes at each stage, whereby a drive current at each of said plurality of digital logic stages is generated as the sum of unequal individual drive currents of each slice at each particular stage; and a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level, wherein said individual drive currents at each slice at each particular stage are weighted by predetermined factors, and wherein a selection of transmitter current is provided by selection of a single one of said slices for each of a discrete set of transmitter power requirements. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification