Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 8,010,593 B2
• Filed: 12/17/2007
• Issued: 08/30/2011
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): Chea, Philip J
• Application Number:
  US12/002,348
• Publication Number:
  US 20080098095A1
• Time in Patent Office: 1,352 Days
• Field of Search: 709/201, 709/205, 709220-222, 712/15, 712/29
• US Class Current: 709/201
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Claims

1. An adaptable computing engine comprising:

a plurality of configurable computing nodes on an integrated circuit, each configurable computing node having a plurality of computational elements coupled to an interconnection network to exchange data to and from the nodes, the node being configurable to perform a task by changing the interconnections between the plurality of computational elements via the interconnection network;

a plurality of hardware node wrappers, each of the plurality of hardware node wrappers corresponding to one of the plurality of computing nodes, each of the node wrappers providing an interface between the computing node and the node interconnection network, each node wrapper comprising a hardware task manager having hardware to schedule a task to be performed by the computing node, configure the computing node to perform the task and control the flow of data to and from the computing node by assigning ports on the node to perform the task; and

wherein the node interconnection network to allow the exchange of configuration information to and from the computing nodes, the node wrapper to read the configuration information to configure the corresponding computing node to perform a first function and the node wrapper to read the configuration information to reconfigure the corresponding computing node to perform a second function.

2. The computing engine of claim 1, wherein the node wrapper allows data flow control and load balancing between the computing nodes.

3. The computing engine of claim 1, wherein the node wrapper further comprises:

an input pipeline register to receive data structures including the data and the configuration information from the node interconnection network;

a data decoder coupled to the input pipeline register to decode the data structure;

a data aggregator coupled to the data decoder to permit loading the data from the data structure; and

an output pipeline register coupled to the data aggregator to receive the data from the data aggregator.

4. The computing engine of claim 3, wherein the node wrapper further comprises a direct memory access engine to facilitate block moves between memories of the computing node.

5. The computing engine of claim 1, wherein the hardware task manager further accesses a table of multiple tasks, enables the tasks and reconfigures the node for a next task.

6. The computing engine of claim 1, wherein each computing node further comprises:

a computing unit interconnection network coupling each of the plurality of computational units to each other, wherein the plurality of computational units are configurable and comprise at least two different types of computational units.

7. The adaptive computing engine of claim 6, wherein the computational units further comprise a plurality of heterogeneous computational elements interconnected with each other.

8. The adaptive computing engine of claim 7, wherein the computing unit interconnection network has denser interconnections between the computing elements than the interconnections of the node interconnection network between the computing nodes.

9. The adaptive computing engine of claim 7, wherein the computational units are configurable to perform different functions based on switchable interconnections between the plurality of computational elements.

10. The computing engine of claim 1, wherein the node interconnection network allows simultaneous flow of data between the plurality of nodes.

11. The computing engine of claim 1, wherein the node wrapper accepts input of data and performing a task by the computing node in a single clock cycle.

12. A computing engine comprising:

a configurable computing node having a plurality of computational elements coupled to an interconnection network, the node being configurable to perform a task by changing the interconnections between the plurality of computational elements via the interconnection network;

a node interconnection network coupling the computing node to other components of the computing engine, the node interconnection network to allow configuration information to be received by and transmitted from the computing node;

a hardware node wrapper coupled to the computing node, the node wrapper providing an interface between the computing node and the node interconnection network, the node wrapper comprising a hardware task manager having hardware to schedule a task to be performed by the computing node, hardware to control the flow of configuration information to the computing node to configure the computing node to perform the task via changing connections of the interconnection network between computational elements of the computing node, and hardware to control the input and output of data from the computing node to perform the task by assigning ports of the computing node.

13. The computing engine of claim 12, wherein the node interconnection network allows the exchange of data to and from the other components of the computing engine, the other components comprising other computing nodes and a memory.

14. The computing engine of claim 13, wherein the node wrapper to allows data flow control and load balancing between the computing node and other computing nodes.

15. The computing engine of claim 13, wherein the node wrapper further comprises:

an input pipeline register to receive data structures including the data and the configuration information from the node interconnection network;

a data decoder coupled to the input pipeline register to decode the data structure;

a data aggregator coupled to the data decoder to permit loading the data from the data structure; and

an output pipeline register coupled to the data aggregator to receive the data from the data aggregator.

16. The computing engine of claim 15, wherein the node wrapper further comprises a direct memory access engine to facilitate block moves between memories of the computing node.

17. The computing engine of claim 12, wherein the hardware task manager further accesses a table of multiple tasks, enables the tasks and reconfigures the node for a next task.

18. The computing engine of claim 17, wherein the table of multiple tasks classifies the task as idle, suspended, ready and run.

19. The computing engine of claim 12 wherein the other components of the computing engine comprise other computing nodes, each of the computing nodes coupled to a respective hardware node wrapper, the other computing nodes and the computing node located on an integrated circuit.

20. A method of performing a task with a computing node having a plurality of computational elements and an interconnection network, the computing node configurable by changing the interconnections between the plurality of computational elements via the interconnection network to perform a function, the method comprising:

sending configuration information via a computing node interconnection network to a hardware node wrapper coupled to the computing node;

receiving the configuration information and configuring the computing node via the node wrapper by changing the interconnections between the plurality of computation elements via the interconnection network;

scheduling a task for the computing node to perform via hardware of a hardware task manager in the node wrapper;

assigning input and output ports in the node for data necessary to perform the task via the hardware task manager in the node wrapper; and

performing the task via the configured computing node.