Direct memory access in a hybrid computing environment

• US 8,010,718 B2
• Filed: 02/03/2009
• Issued: 08/30/2011
• Est. Priority Date: 02/03/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ceason, Jeffrey M., Carey, James E., Sanders, Philip J., Archer, Charles J.
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): SUN, SCOTT C
• Application Number:
  US12/364,590
• Publication Number:
  US 20100198997A1
• Time in Patent Office: 938 Days
• Field of Search: None
• US Class Current: 710/22
• CPC Class Codes: G06F 13/30 with priority control

Abstract

Direct memory access (‘DMA’) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol; segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments; pinning, by the system level message passing module, the memory segments against paging; and asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.

Claims

1. A method of direct memory access (‘

DMA’

) in a hybrid computing environment, the hybrid computing environment comprising a host computer having a host computer architecture, an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, the method comprising;

identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol;

segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments;

pinning, by the system level message passing module, the memory segments against paging; and

asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.

2. The method of claim 1 further comprising:

specifying, by the system level message passing module, the number of memory segments in dependence upon a quantity of available real memory, a quantity of available pinning resources, and a quantity of available DMA bandwidth.

3. The method of claim 1 further comprising:

specifying, by the system level message passing module, a size of the memory segments in dependence upon the time required to pin a memory segment and the time required to effect a DMA transfer of a memory segment.

4. The method of claim 1 further comprising:

failing, by the system level message passing module, to pin a first memory segment on the host computer for a DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, all data in the buffer according to a data communications protocol other than the DMA protocol.

5. The method of claim 1 further comprising:

failing, by the system level message passing module, to pin a memory segment on the host computer for a second or later DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, according to a data communications protocol other than the DMA protocol, data only from the segment which failed to pin.

6. The method of claim 1 further comprising:

failing, by the system level message passing module, to pin a memory segment on the accelerator for a particular DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer according to a data communications protocol other than the DMA protocol, data only for the particular DMA transfer for which the segment failed to pin.

7. A hybrid computing environment for direct memory access (‘

DMA’

), the hybrid computing environment comprising a host computer having a host computer architecture, an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, the hybrid computing environment further comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of;

identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol;

segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments;

pinning, by the system level message passing module, the memory segments against paging; and

asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.

8. The hybrid computing environment of claim 7 further comprising computer program instructions capable of:

specifying, by the system level message passing module, the number of memory segments in dependence upon a quantity of available real memory, a quantity of available pinning resources, and a quantity of available DMA bandwidth.

9. The hybrid computing environment of claim 7 further comprising computer program instructions capable of:

specifying, by the system level message passing module, a size of the memory segments in dependence upon the time required to pin a memory segment and the time required to effect a DMA transfer of a memory segment.

10. The hybrid computing environment of claim 7 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a first memory segment on the host computer for a DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, all data in the buffer according to a data communications protocol other than the DMA protocol.

11. The hybrid computing environment of claim 7 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a memory segment on the host computer for a second or later DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, according to a data communications protocol other than the DMA protocol, data only from the segment which failed to pin.

12. The hybrid computing environment of claim 7 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a memory segment on the accelerator for a particular DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer according to a data communications protocol other than the DMA protocol, data only for the particular DMA transfer for which the segment failed to pin.

13. A computer program product for direct memory access (‘

DMA’

) in a hybrid computing environment, the hybrid computing environment comprising a host computer having a host computer architecture, an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, the computer program product disposed in a computer readable, recordable storage medium, the computer program product comprising computer program instructions capable of;

identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol;

segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments;

pinning, by the system level message passing module, the memory segments against paging; and

asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.

14. The computer program product of claim 13 further comprising computer program instructions capable of:

specifying, by the system level message passing module, the number of memory segments in dependence upon a quantity of available real memory, a quantity of available pinning resources, and a quantity of available DMA bandwidth.

15. The computer program product of claim 13 further comprising computer program instructions capable of:

specifying, by the system level message passing module, a size of the memory segments in dependence upon the time required to pin a memory segment and the time required to effect a DMA transfer of a memory segment.

16. The computer program product of claim 13 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a first memory segment on the host computer for a DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, all data in the buffer according to a data communications protocol other than the DMA protocol.

17. The computer program product of claim 13 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a memory segment on the host computer for a second or later DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer to the accelerator, according to a data communications protocol other than the DMA protocol, data only from the segment which failed to pin.

18. The computer program product of claim 13 further comprising computer program instructions capable of:

failing, by the system level message passing module, to pin a memory segment on the accelerator for a particular DMA transfer from the host computer to the accelerator; and

sending, by the system level message passing module from the host computer according to a data communications protocol other than the DMA protocol, data only for the particular DMA transfer for which the segment failed to pin.