Data processing apparatus and shared memory accessing method

• US 8,010,746 B2
• Filed: 09/12/2008
• Issued: 08/30/2011
• Est. Priority Date: 10/16/2007
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Matsuki, Toshihisa
• Primary Examiner(s): Yu, Jae U
• Application Number:
  US12/232,208
• Publication Number:
  US 20090100225A1
• Time in Patent Office: 1,082 Days
• Field of Search: 711/118, 711/147, 711/153, 709/247
• US Class Current: 711/118
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory

Abstract

The present invention provides a data processing apparatus for processing data by causing a plurality of function blocks to share a single shared memory, the data processing apparatus including: a memory controller configured to cause the plurality of function blocks to write and read data to/and from the shared memory in response to requests from any one of the function blocks; a cache memory; and a companding section configured to compress the data to be written to the cache memory while expanding the data read therefrom.

Claims

1. A data processing apparatus for processing data by causing a plurality of function blocks to share a single shared memory, said data processing apparatus comprising:

a memory controller configured to cause said plurality of function blocks to write and read data to/and from said shared memory in response to requests from any one of said function blocks;

a cache memory; and

a companding section configured to compress the data to be written to said cache memory while expanding the data read therefrom;

wherein

said memory controller checks to determine which of a plurality of areas in said shared memory a write and/or read request from any one of said function blocks corresponds to,

if said write and/or read request from one of said function blocks is found corresponding to a cache area of said shared memory, then said memory controller causes the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that the data is subjected to a caching process involving the use of said cache memory,

if said write and/or read request from one of said function blocks is found corresponding to a compressed cache area of said shared memory, then said memory controller causes the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is compressed by said companding section before being subjected to a caching process involving the use of said cache memory, and

if said write and/or read request from one of said function blocks is found corresponding to a non-cache area of said shared memory, then said memory controller stops the use of said cache memory while causing the data to be written and/or read to/and from said shared memory,

if said write and/or read request from one of said function blocks is found corresponding to said cache area of said shared memory, then said memory controller under control of a host controller causes the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that said caching process is stopped or that the data is compressed by said companding section before being subjected to said caching process involving the use of said cache memory; and

/or

if said write and/or read request from one of said function blocks is found corresponding to said compressed cache area of said shared memory, then said memory controller under control of said host controller causes the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is not compressed by said companding section before being subjected to said caching process or that the use of said cache memory is stopped.

2. The data processing apparatus according to claim 1, wherein said memory controller checks an address of said write and/or read request from one of said function blocks against a memory map of said shared memory in order to determine which of the areas in said shared memory said write and/or read request corresponds to.

3. The data processing apparatus according to claim 1, wherein said memory controller determines which of said function blocks has issued said write and/or read request, before determining which of the areas in said shared memory said write and/or read request from the function block corresponds to.

4. The data processing apparatus according to claim 1, wherein said shared memory is furnished with said cache area, said compressed cache area, and said non-cache area regarding each of said function blocks.

5. The data processing apparatus according to claim 1, wherein said data is constituted by image data;

said plurality of function blocks record said image data to said shared memory before successively processing the recorded data; and

said non-cache area is an area to which to record said image data.

6. A shared memory accessing method for use with a data processing apparatus for processing data by causing a plurality of function blocks to share a single shared memory, said shared memory accessing method comprising the steps of:

compressing the data to be written to a cache memory while expanding the data read therefrom;

determining which of a plurality of areas in said shared memory a write and/or read request from any one of said function blocks corresponds to;

if in said determining step said write and/or read request from one of said function blocks is found corresponding to a cache area of said shared memory, then causing the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that the data is subjected to a caching process involving the use of said cache memory;

if in said determining step said write and/or read request from one of said function blocks is found corresponding to a compressed cache area of said shared memory, then causing the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is compressed in a companding step before being subjected to a caching process involving the use of said cache memory; and

if in said determining step said write and/or read request from one of said function blocks is found corresponding to a non-cache area of said shared memory, then stopping the use of said cache memory while causing the data to be written and/or read to/and from said shared memory,

if said write and/or read request from one of said function blocks is found corresponding to said cache area of said shared memory, then a memory controller under control of a host controller causes the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that said caching process is stopped or that the data is compressed by a companding section before being subjected to said caching process involving the use of said cache memory; and

/or

if said write and/or read request from one of said function blocks is found corresponding to said compressed cache area of said shared memory, then said memory controller under control of said host controller causes the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is not compressed by said companding section before being subjected to said caching process or that the use of said cache memory is stopped.