Synchronous flash memory with status burst output

• US 8,010,767 B2
• Filed: 09/30/2009
• Issued: 08/30/2011
• Est. Priority Date: 07/28/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): Elmore; Reba I
• Application Number:
  US12/570,570
• Publication Number:
  US 20100088484A1
• Time in Patent Office: 699 Days
• Field of Search: 711/103, 711/105, 711/168, 365/203, 365/233
• US Class Current: 711/168
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Claims

1. A method of operating a memory device, comprising:

setting a burst length for the memory device;

setting a clock latency period for the memory device;

receiving a read register command received during a write operation; and

outputting data from a register for a period equal to the burst length,

wherein, in response to the register read command, the data output from the register is delayed for the clock latency period.

2. The method of claim 1, wherein setting a burst length comprises establishing a read burst length of x-cycles.

3. The method of claim 2, wherein data is output from the register on x-consecutive clock cycles.

4. The method of claim 1, wherein the burst length and the clock latency are stored in a mode register.

5. The method of claim 4, and further comprising using the mode register to define a specific operation of the memory device including selecting at least one of the burst length, a burst type, the clock latency period, and an operating mode.

6. The method of claim 1, and further comprising monitoring a status register of the memory device during write, erase, and protect operations, the status register outputting a status of an internal state machine during a memory operation.

7. The method of claim 1, wherein outputting data further comprises outputting data from the register on data communication connections of the memory device.

8. A method of operating a memory device, comprising:

programming the memory device with a burst length and clock latency stored in a mode register;

receiving a status request during a memory operation;

outputting a memory device status in response to the status request, wherein the outputting is performed on a number of clock cycles equal to the burst length; and

in response to the status request, delaying output of the memory device status for the clock latency period.

9. The method of claim 8, wherein outputting the memory device status further comprises outputting from a status register a status of an internal state machine during a memory operation.

10. The method of claim 8, wherein programming a burst length comprises establishing a read burst length of x-cycles.

11. The method of claim 10, wherein programming a clock latency comprises establishing a clock latency of y-cycles.

12. A memory device comprising:

an array of memory cells;

a register;

a clock signal input connection; and

control circuitry to provide data from the register on an output connection in response to a register read command, the control circuitry outputting the data by;

setting a burst length for the data to be output from the register;

setting a clock latency period for data to be output from the register;

receiving the read register command during a memory device operation; and

outputting data from the register for a period equal to the burst length,

wherein, in response to the register read command, the data output from the register is delayed for the clock latency period.

13. The memory device of claim 12, wherein the control circuitry is further adapted to set a burst length of x-cycles.

14. The memory device of claim 13, wherein the control circuitry is further adapted to output data from the register on x-consecutive clock cycles.

15. The memory device of claim 12, wherein the control circuitry is further adapted to use a mode register to define a specific operation of the memory device including selecting at least one of the burst length, a burst type, the clock latency period, and an operating mode.

16. The memory device of claim 12, wherein the control circuitry is further adapted to monitor a status register of the memory device during write, erase, and protect operations, the status register containing a status of an internal state machine during a memory operation.