Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
First Claim
1. A method for analyzing a scan chain of a device under test, comprising:
- setting an environmental variable of the scan chain to a first value, and then shifting a non-constant sequence pattern through the scan chain to determine whether an unexpected toggle pattern is output from the scan chain;
setting the environmental variable to a second value, and then shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and
at least when the scan chain both i) outputs the unexpected toggle pattern at the first value of the environmental variable, and ii) fails to output the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a number of possible hold time faults in the scan chain based on results of a first number of scan tests.
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Accused Products
Abstract
In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.
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Citations
23 Claims
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1. A method for analyzing a scan chain of a device under test, comprising:
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setting an environmental variable of the scan chain to a first value, and then shifting a non-constant sequence pattern through the scan chain to determine whether an unexpected toggle pattern is output from the scan chain; setting the environmental variable to a second value, and then shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and at least when the scan chain both i) outputs the unexpected toggle pattern at the first value of the environmental variable, and ii) fails to output the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a number of possible hold time faults in the scan chain based on results of a first number of scan tests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for analyzing a scan chain of a device under test, comprising:
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setting an environmental variable of the scan chain to a first value, and then shifting a non-constant sequence pattern through the scan chain to determine whether an unexpected toggle pattern is output from the scan chain; setting the environmental variable to a second value, and then shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and when the scan chain both i) outputs the unexpected toggle pattern at the first value of the environmental variable, and ii) outputs the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a location of at least one possible hold time fault in the scan chain based on results of a number of scan tests, wherein the second number of scan tests are performed using the first and second values of the environmental variable. - View Dependent Claims (20)
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21. A method for determining a number of possible hold time faults in a scan chain of a device under test, comprising:
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setting an environmental variable of the scan chain to a value believed to cause a hold time fault in the scan chain; and
thenshifting a pattern through the scan chain, the pattern having a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain; and determining the number of possible hold time faults in the scan chain as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. - View Dependent Claims (22, 23)
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Specification