Capping layers for metal oxynitride TFTS

• US 8,012,794 B2
• Filed: 06/29/2009
• Issued: 09/06/2011
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ye, Yan
• Primary Examiner(s): Toledo; Fernando L
• Application Number:
  US12/493,718
• Publication Number:
  US 20100001274A1
• Time in Patent Office: 799 Days
• Field of Search: 257/43, 257/57, 257/E21.414
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.

Claims

1. A thin film transistor fabrication method, comprising:

depositing a semiconductor layer over a thin film transistor stack comprising a substrate, a gate electrode, and a gate dielectric layer, the semiconductor layer comprising an oxynitride compound that comprises nitrogen, oxygen, and one or more elements selected from zinc, indium, tin, gallium, cadmium, and combinations thereof;

depositing a conductive layer over the semiconductor layer;

etching the conductive layer to define source and drain electrodes and to expose a portion of the semiconductor layer between the source and drain electrodes defined as the active channel; and

depositing a capping layer over the exposed semiconductor layer by flowing N₂O and SiH₄ gas into a processing chamber at a ratio of N₂O and SiH₄ of between about 20;

1 to about 40;

1.

4. The method of claim 1, further comprising flowing N₂ gas along with the N₂O and SiH₄ gases.

5. The method of claim 1, wherein the capping layer comprises silicon oxide.

6. The method of claim 5, further comprising a silicon nitride layer deposited on the silicon oxide capping layer.

7. The method of claim 1, wherein the capping layer comprises a plurality of layers with silicon oxide deposited adjacent the semiconductor layer.

8. The method of claim 1, further comprising exposing the gate dielectric layer to one or more of N₂O gas or a plasma formed from N₂O gas.

9. The method of claim 1, wherein the semiconductor layer is deposited by sputtering.

10. The method of claim 9, wherein the semiconductor layer comprises a dopant.

2. A thin film transistor fabrication method, comprising:

depositing a semiconductor layer over a thin film transistor stack comprising a substrate, a gate electrode, and a gate dielectric layer, the semiconductor layer comprising nitrogen, oxygen, and one or more elements selected from zinc, indium, tin, gallium, cadmium, and combinations thereof;

depositing a conductive layer over the semiconductor layer;

etching the conductive layer to define source and drain electrodes and to expose a portion of the semiconductor layer between the source and drain electrodes defined as the active channel; and

depositing a capping layer over the exposed semiconductor layer by flowing N₂O and SiH₄ gas into a processing chamber at a ratio of N₂O and SiH₄ of between about 20;

1 to about 40;

1 and flowing PH₃ gas along with the N₂O and SiH₄ gases.

3. The method of claim 2, wherein a ratio of PH₃ gas to a total amount of hydrogen flowed into the processing chamber is between about 1:

1000 to about 1;

150.

11. A thin film transistor fabrication method, comprising:

depositing a semiconductor layer over a thin film transistor stack comprising a substrate, a gate electrode, and a gate dielectric layer, the semiconductor layer comprising nitrogen, oxygen, and one or more elements selected from zinc, indium, tin, gallium, cadmium, and combinations thereof;

depositing a conductive layer over the semiconductor layer;

etching the conductive layer to define source and drain electrodes and to expose a portion of the semiconductor layer between the source and drain electrodes defined as the active channel; and

depositing a silicon oxide layer over the exposed semiconductor layer in the active channel to partially fill the active channel, the depositing comprising flowing N₂O, SiH₄, and PH₃ gas into a processing chamber to obtain a chamber pressure of about 500 mTorr to about 2.5 Torr and applying an RF bias and to a gas distribution showerhead in the processing chamber is between about 1.16×

10<sup>−

6</sup> W/cm² to about 4.63×

10<sup>−

3</sup> W/cm².

12. The method of claim 11, wherein a flow ratio of N₂O and SiH₄ is between about 20:

1 to about 40;

1.

13. The method of claim 12, wherein a ratio of PH₃ gas to a total amount of hydrogen flowed into the processing chamber is between about 1:

1000 to about 1;

150.

14. The method of claim 11, further comprising flowing N₂ gas along with the N₂O and SiH₄ gases.

15. The method of claim 11, further comprising exposing the gate dielectric layer to one or more of N₂O gas or a plasma formed from N₂O gas.

16. The method of claim 11, wherein the semiconductor layer is deposited by sputtering.

17. The method of claim 16, wherein the silicon oxide layer is deposited at a temperature between about 200 degrees Celsius and about 350 degrees Celsius.