Multi-directional trenching of a die in manufacturing superjunction devices

• US 8,012,806 B2
• Filed: 02/15/2008
• Issued: 09/06/2011
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: IceMOS Technology Ltd
• Original Assignee: IceMOS Technology Ltd
• Inventors: Sugiura, Kenji, Griffin, Hugh J., Ishiguro, Takeshi
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/031,895
• Publication Number:
  US 20090085147A1
• Time in Patent Office: 1,299 Days
• Field of Search: 438106-132, 438460-465, 438/E21.545
• US Class Current: 438/113
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Claims

1. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer, the semiconductor wafer including at least one die;

(b) forming at least one first trench in the at least one die, the at least one first trench having a first orientation and defining a first area; and

(c) forming at least one second trench in the at least one die, the at least one second trench having a second orientation that is different from the first orientation, the at least one second trench defining a second area such that a ratio of the first area to the second area is about one-to-one.

2. The method of claim 1, further comprising:

(d) forming at least one additional trench in the at least one die, each additional trench having an orientation that is different from at least one of the first orientation and the second orientation.

3. The method of claim 1, wherein the steps (a)-(c) are performed sequentially.

4. The method of claim 1, wherein the steps (b) and (c) are performed concurrently.

5. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.

6. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.

7. A superjunction device formed by the method of claim 1.

8. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer, the semiconductor wafer including at least one die;

(b) forming a first plurality of trenches in the at least one die, each of the first plurality of trenches having a first orientation, the first plurality of trenches defining a first area; and

(c) forming a second plurality of trenches in the at least one die, each of the second plurality of trenches having a second orientation that is different from the first orientation, the second plurality of trenches defining a second area such that a ratio of the first area to the second area is about one-to-one.

9. The method of claim 8, wherein

(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being different from at least one other of the first plurality of trenches;

and

(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being different from at least one other of the second plurality of trenches.

10. The method of claim 8, wherein

(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical;

and

(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being identical.

11. The method of claim 8, wherein the steps (a)-(c) are performed sequentially.

12. The method of claim 8, wherein the steps (b) and (c) are performed concurrently.

13. The method of claim 8, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.

14. The method of claim 8, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.

15. A superjunction device formed by the method of claim 8.