Process to make high-K transistor dielectrics

• US 8,012,824 B2
• Filed: 06/16/2006
• Issued: 09/06/2011
• Est. Priority Date: 04/18/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yao, Liang-Gi, Chen, Shih-Chang, Wang, Ming-Fang, Liang, Mong-Song
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US11/454,596
• Publication Number:
  US 20060246698A1
• Time in Patent Office: 1,908 Days
• Field of Search: 438/240, 438286-287
• US Class Current: 438/240
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/02153 the material containing titanium, e.g. TiSiOx
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31616 Deposition of Al2O3
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Claims

1. A method of reducing impurities in a high-k dielectric layer, comprising the steps of:

providing a substrate having STIs formed therein;

forming a high-k dielectric layer between the STIs;

the high-k dielectric layer having impurities therein and being formed by an ALCVD process;

annealing the high-k dielectric layer to reduce the impurities within the high-k dielectric layer without additional oxidation of the high-k dielectric layer; and

forming a gate layer upon the annealed high-k dielectric layer.

2. The method of claim 1, wherein the substrate is a silicon substrate;

and the high-k dielectric layer is a metal oxide or a metal silicate and is formed by either an MOCVD process or an ALCVD process.

3. The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO₂, ZrO₂, La₂O₃, Y₂O₃, Al₂O₃, TiO₂, HfSi_xO_y, ZrSi_xO_y, LaSi_xO_y, YSi_xO_y, AlSi_xO_y and TiSi_xO_y.

4. The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO₂, ZrO₂, Al₂O₃, HfSi_xO_y and ZrSi_xO_y.

5. The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 280 to 820°

C. for from about 0.5 to 300 seconds.

6. The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 300 to 800°

C. for from about 2 to 100 seconds.

7. The method of claim 1, wherein the high-k dielectric layer anneal is a furnace anneal process conducted at a temperature of from about 300 to 800°

C. for from about 5 to 300 minutes.

8. The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either rapid thermal processing or a furnace anneal process.

9. The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either a rapid thermal processing or a furnace anneal process using an ambient selected from the group consisting of H₂, N₂, H₂/N₂, H₂/O₂, O₂/N₂, He and Ar.

10. The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either a rapid thermal processing or a furnace anneal process using an ambient selected from the group consisting of H₂/N₂ and O₂/N₂.

11. The method of claim 1, wherein the STIs are comprised of a material selected from the group consisting of thermal oxide, SACVD oxide and HDP-CVD oxide.

12. The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 280 to 820°

C. using either rapid thermal processing or a furnace anneal process with an ambient selected from the group consisting of H₂, N₂, H₂/N₂, H₂/O₂, O₂/N₂.

13. The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 300 to 800°

C. using either rapid thermal processing or a furnace anneal process with an ambient selected from the group consisting of H₂/N₂ and O₂/N₂.

14. The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 5 to 200 Å

.

15. The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 20 to 100 Å

.

16. The method of claim 1, wherein the gate layer comprised of a material selected from the group consisting of polysilicon, TaN/W, TiN/W, TaN/Al and TiN/Al.

17. The method of claim 1, wherein the gate layer is comprised of polysilicon.

18. The method of claim 1, wherein the gate layer has a thickness of from about 100 to 3000 Å

.

19. The method of claim 1, wherein the gate layer has a thickness of from about 500 to 2000 Å

.