Recess gate transistor

• US 8,012,828 B2
• Filed: 10/14/2008
• Issued: 09/06/2011
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Woo, Dongsoo, Kang, Sangbom, Hwang, Heedon, Min, Ji-Young, Lee, Si-Hyung, Choi, Si-Young
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Crawford; Latanya
• Application Number:
  US12/251,054
• Publication Number:
  US 20090173994A1
• Time in Patent Office: 1,057 Days
• Field of Search: 438/243, 438/259, 438/589, 438/277, 438/269, 438/270, 438/258, 257/211, 257/330, 257/192, 257/530, 257/E29.255, 257/E29.26, 257/E29.258, 257/E21.655, 257/E21.345, 257/E21.427, 257/E21.43, 257/E21.429, 257/E21.428, 257/E21.419, 257/E21.384, 257/E21.41, 257/E27.084, 257/E21.42
• US Class Current: 438/259
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a source and drain layer;

forming a recess and depositing a gate insulation layer therein;

forming a first conductive layer on the gate insulation layer;

forming a first conductive layer pattern by recessing the first conductive layer;

forming a second conductive layer on the first conductive layer pattern;

forming a second conductive layer pattern by patterning the second conductive layer;

depositing an insulating layer on the second conductive layer pattern;

etching the insulating layer to expose the second conductive layer pattern and forming a spacer layer adjacent to the source and drain layer; and

forming a third conductive layer on the second conductive layer pattern and the spacer layer.

2. The method of claim 1, wherein the first conductive layer pattern is metallic and the second conductive layer pattern is polysilicon.

3. The method of claim 1, wherein the first conductive layer pattern and the second conductive layer pattern are both metallic.

4. The method of claim 1, wherein the source and drain layer and the recess form a part of an NMOS device and the first conductive layer pattern has a workfunction equal to or greater than a workfunction of the second conductive layer pattern.

5. The method of claim 1, wherein the source and drain layer and the recess is part of a PMOS device and the first conductive layer pattern has a workfunction equal to or less than a workfunction of the second conductive layer pattern.

6. The method of claim 1, wherein the first conductive layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

7. The method of claim 1, wherein the spacer layer is an oxide or a nitride.

8. The method of claim 1, wherein the first conductive layer pattern is a metal and the second conductive layer pattern is a polysilicon.

9. The method of claim 1, wherein the first conductive layer pattern and the second conductive layer pattern are both metallic.