High mobility CMOS circuits

• US 8,013,392 B2
• Filed: 09/28/2007
• Issued: 09/06/2011
• Est. Priority Date: 11/06/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Gluschenkov, Oleg G., Doris, Bruce B., Zhu, Huilong
• Primary Examiner(s): Gebremariam; Samuel A
• Application Number:
  US11/863,757
• Publication Number:
  US 20080237720A1
• Time in Patent Office: 1,439 Days
• Field of Search: 257/351, 257/368, 257/369, 257/635, 257/637, 257/639
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

Claims

1. A semiconductor circuit comprising a substrate;

a plurality of field effect transistors comprising pFETS and nFETS formed on the substrate, the plurality of field effect transistors including a first portion of field effect transistors and a second portion of field effect transistors;

a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transistors; and

a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors,

wherein the first thickness is different than the second thickness,

wherein the first determined stress is different than the second determined stress,

wherein;

the first portion of the plurality of field effect transistors have spacings between adjacent field effect transistors that fall within a first defined spacing range; and

the second portion of the plurality of field effect transistors have spacings between adjacent field effect transistors that fall within a second defined spacing range,

wherein the first defined spacing range is different than the second defined spacing range, and

wherein at least one of;

the first stress layer is applied over an entire surface containing the plurality of field effect transistors;

the first stress layer imparts the first determined stress to a channel region of the first portion of the plurality of field effect transistors; and

the first stress layer is formed on top of the first portion of the plurality of field effect transistors and the second stress layer is formed on top of the second portion of the plurality of field effect transistors.

2. The semiconductor circuit according to claim 1, wherein:

the first defined spacing range is less than the second defined spacing range; and

the first thickness is less than the second thickness.

3. The semiconductor circuit according to claim 1, wherein:

the first defined spacing range is less than the second defined spacing range; and

the first thickness is less than the second thickness.

4. The semiconductor circuit according to claim 1, wherein:

the first defined spacing range is 130 nanometers or less; and

the first thickness is between 20 and 50 nanometers.

5. The semiconductor circuit according to claim 4, wherein:

the second defined spacing range is greater than 130 nanometers; and

the second thickness is between 50 and 500 nanometers.

6. The semiconductor circuit according to claim 1, wherein the first and second portions of field effect transistors comprise pFETS.

7. The semiconductor circuit according to claim 1, wherein the first and second portions of field effect transistors comprise nFETS.

8. A semiconductor circuit comprising a substrate;

a plurality of field effect transistors comprising pFETS and nFETS formed on the substrate, the plurality of field effect transistors including a first portion of field effect transistors and a second portion of field effect transistors;

the first portion of field effect transistors having a different spacing density than the second portion of field effect transistors;

a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transistors; and

a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors,

wherein the first thickness is different than the second thickness,

wherein the first determined stress is different than the second determined stress, and

wherein at least one of;

the first stress layer is applied over an entire surface containing the plurality of field effect transistors;

the first stress layer imparts the first determined stress to a channel region of the first portion of the plurality of field effect transistors; and

the first stress layer is formed on top of the first portion of the plurality of field effect transistors and the second stress layer is formed on top of the second portion of the plurality of field effect transistors.

9. The semiconductor circuit according to claim 8, wherein the first portion of field effect transistors has a greater spacing density than the second portion of field effect transistors and the first thickness is less than the second thickness.

10. The semiconductor circuit according to claim 9, wherein the first and second portions of field effect transistors comprise pFETS.

11. The semiconductor circuit according to claim 9, wherein the first and second portions of field effect transistors comprise nFETS.

12. A semiconductor circuit comprising a substrate;

a first group of transistors comprising;

nFETs interspersed with pFETs spaced a first spacing density, or pFETs interspersed with nFETs spaced the first spacing density;

a first stress layer having a first thickness and being configured to impart stresses to the first group of transistors;

a second group of transistors comprising;

nFETs interspersed with pFETs spaced a second spacing density, or pFETs interspersed with nFETs spaced the second spacing density; and

a second stress layer having a second thickness and being configured to impart stresses to the second group of transistors,

wherein;

the first spacing density is different than the second spacing density; and

the first thickness is different than the second thickness.

13. The semiconductor circuit according to claim 12, wherein the first thickness is less than the second thickness.

14. The semiconductor circuit according to claim 12, wherein the first spacing density is greater than the second spacing density.

15. The semiconductor circuit according to claim 14, wherein the first thickness is less than the second thickness.

16. The semiconductor circuit according to claim 12, wherein:

the first spacing density utilizes a spacing of 130 nanometers or less; and

the first thickness is between 20 and 50 nanometers.

17. The semiconductor circuit according to claim 12, wherein:

the second spacing density utilizes a spacing of greater than 130 nanometers; and

the second thickness is between 50 and 500 nanometers.

18. The semiconductor circuit according to claim 12, wherein:

the first spacing density utilizes a spacing of 130 nanometers or less and the first thickness is between 20 and 50 nanometers;

the second spacing density utilizes a spacing of greater than 130 nanometers and the second thickness is between 50 and 500 nanometers; and

each nFET is stressed with a tensile stress in a channel region thereof and each pFET is stressed with a compressive stress in a channel region thereof.