SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable

• US 8,013,399 B2
• Filed: 05/15/2009
• Issued: 09/06/2011
• Est. Priority Date: 06/02/2008
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Pouydebasque, Arnaud, Batude, Perrine, Vinet, Maud, Thomas, Olivier
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/466,733
• Publication Number:
  US 20090294861A1
• Time in Patent Office: 844 Days
• Field of Search: 257/49, 257 66- 71, 257/213, 257/288, 257347-352, 257/368, 257/369, 257/393, 257/E27.098, 257/E27.099, 257/E27.1
• US Class Current: 257/393
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.

Claims

1. A static random access memory cell which, on a substrate surmounted by a stack of layers, comprising:

a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and

a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level,

wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region,

the second plurality of transistors is formed;

from a first load transistor and a second load transistor, a first conduction transistor and a second conduction transistor, and

the first load transistor, the second load transistor and the first conduction transistor and the second conduction transistor being formed in a single level of said stack.

2. The static random access memory cell of claim 1, wherein the second plurality of transistors is formed from the first conduction transistor having a gate situated opposite to and coupled to the channel region of the first access transistor, the second conduction transistor having a gate situated opposite to and coupled to the channel region of the second access transistor.

3. The static random access memory cell of claim 1, wherein the second plurality of transistors is formed from the first load transistor having a gate situated opposite to and coupled to the channel region of the first access transistor, the second load transistor having a gate situated opposite to and coupled to the channel region of the second access transistor.

4. The static random access memory cell of claim 1, wherein the first load transistor and the second load transistor are arranged opposite to and coupled to the second conduction transistor and first conduction transistor, respectively.

5. The static random access memory cell of claim 1, wherein the first plurality of transistors further includes at least one third access transistor and at least one fourth access transistor, which are arranged between a third bit line and the first storage node, and between a fourth bit line and the second storage node respectively, the third access transistor and the fourth access transistor having a gate connected to a second word line.

6. The static random access memory cell as claimed in claim 1, wherein said insulating region has an SiO₂ equivalent thickness of between 1 and 50 nanometers.

7. The static random access memory cell as claimed in claim 1, wherein the coupling is such that a variation in potential of said gate electrode results in a variation in the threshold voltage of said channel region.

8. The static random access memory cell as claimed in claim 7, wherein the cell has a supply voltage Vdd, and the coupling is such that a variation in the potential of said gate electrode of more than Vdd makes it possible to obtain a variation in the threshold voltage of said channel region of at least 50 mV.

9. The static random access memory cell as claimed in claim 1, wherein, between said gate electrode and said channel region, said insulating region is formed from a first region containing a first dielectric material having a first dielectric constant k₁, which is opposite source and drain regions, and said insulating region is formed from a second region comprising at least one second dielectric material having a second dielectric constant k₂ such that k₂<

k₁.

10. The static random access memory cell of claim 9, wherein said second region comprises a stacking of said first dielectric material and said second dielectric material.

11. A static random access memory cell which, on a substrate surmounted by a stack of layers, comprising:

a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and

a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level,

wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region, and

said insulating region has an SiO₂ equivalent thickness of between 1 and 50 nanometers.

12. The static random access memory cell of claim 11, wherein the second plurality of transistors is formed from a first conduction transistor and a second conduction transistor, the first conduction transistor having a gate situated opposite to and coupled to the channel region of the first access transistor, the second conduction transistor having a gate situated opposite to and coupled to the channel region of the second access transistor.

13. The static random access memory cell of claim 11, wherein the second plurality of transistors is formed from a first load transistor and a second load transistor, the first load transistor having a gate situated opposite to and coupled to the channel region of the first access transistor, the second load transistor having a gate situated opposite to and coupled to the channel region of the second access transistor.

14. The static random access memory cell of claim 11, wherein the second plurality of transistors is formed:

from a first load transistor and a second load transistor, a first conduction transistor and a second conduction transistor.

15. The static random access memory cell of claim 14, wherein the first load transistor and the second load transistor are arranged opposite to and coupled to the second conduction transistor and first conduction transistor, respectively.

16. The static random access memory cell of claim 14, wherein the first load transistor, the second load transistor and the first conduction transistor and the second conduction transistor being formed in a single level of said stack.

17. The static random access memory cell of claim 11, wherein the first plurality of transistors further includes at least one third access transistor and at least one fourth access transistor, which are arranged between a third bit line and the first storage node, and between a fourth bit line and the second storage node respectively, the third access transistor and the fourth access transistor having a gate connected to a second word line.

18. The static random access memory cell as claimed in claim 11, wherein the coupling is such that a variation in potential of said gate electrode results in a variation in the threshold voltage of said channel region.

19. The static random access memory cell as claimed in claim 18, wherein the cell has a supply voltage Vdd, and the coupling is such that a variation in the potential of said gate electrode of more than Vdd makes it possible to obtain a variation in the threshold voltage of said channel region of at least 50 mV.

20. The static random access memory cell as claimed in claim 11, wherein, between said gate electrode and said channel region, said insulating region is formed from a first region containing a first dielectric material having a first dielectric constant k₁, which is opposite source and drain regions, and said insulating region is formed from a second region comprising at least one second dielectric material having a second dielectric constant k₂ such that k₂<

k₁.

21. The static random access memory cell of claim 20, wherein said second region comprises a stacking of said first dielectric material and said second dielectric material.