Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same
First Claim
Patent Images
1. A circuit having an active clock shielding structure, comprising:
- a logic circuit configured to receive a clock signal and to perform a logic operation based on the clock signal;
a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on a power gating signal;
a clock signal transmission line configured to transmit the clock signal to the logic circuit;
at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line;
a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and
at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line,wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line.
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Accused Products
Abstract
A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.
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Citations
21 Claims
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1. A circuit having an active clock shielding structure, comprising:
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a logic circuit configured to receive a clock signal and to perform a logic operation based on the clock signal; a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on a power gating signal; a clock signal transmission line configured to transmit the clock signal to the logic circuit; at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line; a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line, wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor integrated circuit, comprising:
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a clock signal gating unit configured to control a transmission of a clock signal; a power gating control unit configured to control an activation of a power gating signal or a retention signal to determine a power gating operation; and at least one circuit having an active clock shielding structure configured to receive the clock signal and to operate based on the power gating operation, the at least one circuit having the active clock shielding structure comprising; a logic circuit configured to receive the clock signal and to perform a logic operation based on the clock signal; a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on the power gating signal; a clock signal transmission line configured to transmit the clock signal to the logic circuit; at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line; a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line, wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line. - View Dependent Claims (7, 8, 9, 10)
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11. A circuit having an active clock shielding structure, comprising:
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a logic circuit configured to receive a clock signal and to perform a logic operation based on the clock signal; a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on a power gating signal; a clock signal transmission line configured to transmit the clock signal to the logic circuit; at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line; a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line, wherein the clock signal is transmitted during operation in the active mode and is not transmitted during operation in the sleep mode, and wherein the sleep mode includes a sleep-in mode, a sleep-state mode, and a sleep-out mode. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification