Apparatus and method for efficient level shift
First Claim
Patent Images
1. An apparatus comprising:
- an input stage having a first branch and a second branch;
a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop operates in a first voltage domain;
a level shifter that is coupled to the output terminal of the first flip-flop, wherein the level shifter operates in a second voltage domain, and wherein the level shifter includes;
a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop;
a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop; and
a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the reset stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage; and
a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, and the second branch, and that receives an input signal.
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Abstract
An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.
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Citations
20 Claims
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1. An apparatus comprising:
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an input stage having a first branch and a second branch; a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop operates in a first voltage domain; a level shifter that is coupled to the output terminal of the first flip-flop, wherein the level shifter operates in a second voltage domain, and wherein the level shifter includes; a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop; a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop; and a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the reset stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage; and a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, and the second branch, and that receives an input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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a high voltage rail; a low voltage rail; a control circuit having a first output terminal and a second output terminal, wherein the control circuit is coupled to the low voltage rail; a level shifter having; an input stage having a first branch and a second branch that are each coupled to the high voltage rail; a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop is coupled to the high voltage rail; a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop, wherein the reset stage is coupled to the low voltage rail; a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop, wherein the set stage is coupled to the low voltage rail; and a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the rest stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage, and wherein the second flip-flop is coupled to the low voltage rail; and a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, the second branch, and the first output terminal of the control circuit; a high side driver that is coupled to the output terminal of the first flip-flop; a low side driver that is coupled to the second output terminal of the control circuit; a current sensing circuit that is adapted to receive a current feedback signal; an error amplifier that is adapted to receive a voltage feedback signal; and a summing comparator that is coupled to the current sensing circuit, the voltage sensing circuit, and the control circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. An apparatus comprising:
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a high voltage rail; a low voltage rail; an input stage having; a first resistor that is coupled to the high voltage rail; a first MOS transistor that is coupled to the first resistor at its drain; a second resistor that is coupled to the high voltage rail; and a second MOS transistor that is coupled to the second resistor at its drain; a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first resistor, and wherein the second input terminal of the first flip-flop is coupled to the second resistor, and wherein the first flip-flop is coupled to the high voltage rail; a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop, wherein the reset stage is coupled to the low voltage rail; a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop, wherein the set stage is coupled to the low voltage rail; and a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the rest stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage, and wherein the second flip-flop is coupled to the low voltage rail; and a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, the second branch, and that receives an input signal. - View Dependent Claims (17, 18, 19, 20)
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Specification