Single transistor memory cell

• US 8,014,195 B2
• Filed: 02/06/2009
• Issued: 09/06/2011
• Est. Priority Date: 02/06/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nagoga, Mikhail, Okhonin, Serguei
• Primary Examiner(s): Yoha; Connie C
• Application Number:
  US12/367,154
• Publication Number:
  US 20090201723A1
• Time in Patent Office: 942 Days
• Field of Search: 365/177, 365/222, 365/190, 365/149, 365/230.03
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells

Abstract

A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device is inherently refreshed during hold operations.

Claims

1. An integrated circuit device comprising:

a memory cell including a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and

hold circuitry coupled to the memory cell, the hold circuitry to continually apply a set of hold signals to the gate and between the source region and the drain region of the transistor except during read operations and write operations, wherein the set of hold signals continually hold a data state of the transistor by inherently refreshing the data state, wherein the data state includes at least one of a logic high data state and a logic low data state.

2. The integrated circuit device of claim 1, wherein the transistor retains the data state as long as the hold signals are applied.

3. The integrated circuit device of claim 1, wherein the source region, the body region, and the drain region function as the emitter, the base, and the collector of an inherent bipolar transistor, respectively.

4. The integrated circuit device of claim 1, wherein:

when the body region of the transistor is in the logic high data state, the set of hold signals cause bipolar current to flow in the body region; and

when the body region of the transistor is in the logic low data state, the set of hold signals fail to cause bipolar current to flow in the body region.

5. The integrated circuit device of claim 1, wherein the set of hold signals include a first potential applied to the gate, and a second potential applied between the source region and the drain region.

6. The integrated circuit device of claim 5, wherein the first potential includes a voltage of approximately −

0.7 volts.

7. The integrated circuit device of claim 5, wherein the second potential includes a voltage approximately in a range of 1.5 volts to 3.2 volts.

8. The integrated circuit device of claim 5, wherein the second potential includes a voltage of approximately 2.3 volts.

9. The integrated circuit device of claim 5, wherein:

when the body region of the transistor is in the logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the body region and the second potential difference causes bipolar current to flow in the body region resulting from the increase of majority carriers in the body region due to impact ionization; and

when the body region of the transistor is in the logic low data state, the second potential is less than the threshold, wherein the flow of bipolar current is absent in the body region.

10. The integrated circuit device of claim 1, wherein the gate is disposed over a first portion of the body region.

11. The integrated circuit device of claim 10, wherein the source region adjoins a second portion of the body region that is adjacent the first portion and separates the source region from the first portion.

12. The integrated circuit device of claim 11, wherein the drain region adjoins a third portion of the body region that is adjacent the first portion and separates the drain region from the first portion.

13. The integrated circuit device of claim 1, wherein one or more of the source region and the drain region include a doped region shaped so that a farthermost boundary of the doped region is separated from a portion of the body region underlying the gate.

14. The integrated circuit device of claim 1, wherein the body region includes a first type of semiconductor material and the source region and drain region include a second type of semiconductor material.

15. The integrated circuit device of claim 14, wherein the source region includes a lightly doped region.

16. The integrated circuit device of claim 14, wherein the source region includes a highly doped region.

17. The integrated circuit device of claim 14, wherein the source region includes a lightly doped region and a highly doped region.

18. The integrated circuit device of claim 14, wherein the drain region includes a lightly doped region.

19. The integrated circuit device of claim 14, wherein the drain region includes a highly doped region.

20. The integrated circuit device of claim 14, wherein the drain region includes a lightly doped region and a highly doped region.

21. An integrated circuit device comprising:

a memory cell consisting essentially of one transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and

hold circuitry coupled to the memory cell to apply hold voltages to the transistor except during read operations and write operations, the hold voltages inherently refreshing at least one of a logic high data state and a logic low data state and holding a data state of the transistor, the hold voltages including a first potential applied to the gate, a second potential applied to the source region, and a third potential applied to the drain region.

22. The integrated circuit device of claim 21, wherein the transistor retains the data state as long as the hold voltages are applied.

23. The integrated circuit device of claim 21, wherein the body region functions as an inherent bipolar transistor.

24. The integrated circuit device of claim 21, wherein, when the body region is in the logic high data state, the hold voltages cause bipolar current to flow in the body region.

25. The integrated circuit device of claim 21, wherein, when the body region is in the logic low data state, the hold voltages fail to cause bipolar current to flow in the body region.

26. The integrated circuit device of claim 21, wherein the hold voltages include a first potential applied to the gate, and a second potential applied between the source region and the drain region.

27. The integrated circuit device of claim 26, wherein the first potential includes a voltage of approximately −

0.7 volts.

28. The integrated circuit device of claim 26, wherein the second potential includes a voltage approximately in a range of 1.5 volts to 3.2 volts.

29. The integrated circuit device of claim 26, wherein the second potential includes a voltage of approximately 2.3 volts.

30. The integrated circuit device of claim 26, wherein:

when the body region of the transistor is in the logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the body region and the second potential difference causes bipolar current to flow in the body region as a result of impact ionization due to the presence of minority carriers in the body region; and

when the body region of the transistor is in the logic low data state, the second potential is less than the threshold, wherein the flow of bipolar current is absent in the body region.

31. An integrated circuit device comprising:

a memory cell including a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and

hold circuitry coupled to the memory cell, the hold circuitry to apply holding potentials to the gate and between the source region and the drain region of the transistor except during read operations and write operations, wherein the holding potentials hold a data state of the transistor written during a preceding write operation causing the transistor to retain the data state as the holding potentials are applied, wherein the same holding potentials inherently refresh at least one of a logic high data state and a logic low data state.

32. The integrated circuit device of claim 31, wherein the transistor retains the data state as long as the holding potential is applied.

33. The integrated circuit device of claim 31, wherein, when the body region is in the logic high data state, the holding potential causes bipolar current to flow in the body region.

34. The integrated circuit device of claim 33, wherein, when the body region is in the logic low data state, the holding potential prevents bipolar current flow in the body region.

35. The integrated circuit device of claim 31, wherein the holding potential includes a first potential applied to the gate, and a second potential applied between the source region and the drain region.

36. The integrated circuit device of claim 35, wherein the first potential includes a voltage of approximately −

0.7 volts.

37. The integrated circuit device of claim 35, wherein the second potential includes a voltage approximately in a range of 2.2 volts to 2.6 volts.

38. The integrated circuit device of claim 35, wherein:

when the body region of the transistor is in the logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the body region and the second potential difference causes bipolar current to flow in the body region resulting from the increase of majority carriers in the body region due to impact ionization; and

when the body region of the transistor is in the logic low data state, the second potential is less than the threshold and prevents the flow of bipolar current.

39. A method for continually holding a data state of a memory cell, the memory cell consisting essentially of a transistor configured to include a gate, a floating body, and a source and a drain adjacent the floating body, the method comprising continually applying a set of hold signals to the gate and between the source and the drain of the memory cell except during read operations and write operations, wherein the set of hold signals hold a data state of the memory cell by inherently refreshing the data state, wherein the data state includes at least one of a logic high data state and a logic low data state.

40. The method of claim 39, wherein the hold signals cause the transistor to retain the data state as long as the hold signals are applied.

41. The method of claim 39, wherein the body region functions as an inherent bipolar transistor.

42. The method of claim 39, wherein:

when the floating body of the transistor is in the logic high data state, the set of hold signals cause bipolar current to flow in the floating body; and

when the floating body of the transistor is in the logic low data state, the set of hold signals fail to cause bipolar current to flow in the floating body.

43. The method of claim 39, wherein applying the set of hold signals comprises applying a first potential to a gate of the transistor and applying a second potential between a source region and a drain region of the transistor.

44. The method of claim 43, wherein the first potential includes a voltage of approximately −

0.7 volts.

45. The method of claim 43, wherein the second potential includes a voltage approximately in a range of 2.2 volts to 2.6 volts.

46. The method of claim 43, wherein the second potential includes a voltage of approximately 2.3 volts.

47. The method of claim 43, wherein:

when the floating body of the transistor is in the logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the floating body and the second potential difference causes bipolar current to flow in the floating body resulting from the increase of majority carriers in the floating body due to impact ionization; and

when the floating body of the transistor is in the logic low data state, the second potential is less than the threshold, wherein the flow of bipolar current is absent in the floating body.

48. A method for continually holding a data state of a memory cell, the memory cell consisting essentially of a transistor configured to include a floating body, the method comprising:

continually applying a first potential to a gate of the memory cell except during read operations and write operations; and

continually applying a second potential across a source region and a drain region of the memory cell except during read operations and write operations;

wherein the first potential and the second potential continually hold a data state previously written to the memory cell by inherently refreshing the data state, wherein the data state includes at least one of a logic high data state and a logic low data state.

49. The method of claim 48, wherein, when the floating body is in the logic high data state, the first and second potential cause bipolar current to flow in the floating body.

50. The method of claim 49, wherein, when the floating body is in the logic low data state, the first and second potential prevent bipolar current flow in the floating body.

51. The method of claim 48, wherein the first potential includes a voltage of approximately −

0.7 volts.

52. The method of claim 48, wherein the second potential includes a voltage approximately in a range of 2.2 volts to 2.6 volts.

53. A method for continually holding a data state of a memory cell, the memory cell consisting essentially of a transistor configured to include a gate, a floating body, and a source and a drain adjacent the floating body, the method comprising continually applying holding potentials to the gate and between the source and the drain of the memory cell during all clock cycles except read cycles and write cycles, wherein the holding potentials continually hold a data state of the memory cell written during a preceding write operation causing the memory cell to retain the data state as long as the holding potential is applied, wherein the same holding potential inherently refreshes at least one of a logic high data state and a logic low data state.

54. An integrated circuit device comprising:

a memory cell consisting essentially of one transistor, the transistor comprising,

a gate;

an electrically floating body region; and

a source region and a drain region adjacent the body region; and

hold circuitry coupled to the memory cell, the hold circuitry to continually apply holding potentials to the gate and between the source region and the drain region of the transistor except during read operations and write operations, wherein the holding potentials hold a data state of the transistor written during a preceding write operation and causes the transistor to retain the data state as long as the holding potentials are applied, wherein the same holding potential inherently refreshes at least one of a plurality of data states.

55. The integrated circuit device of claim 54, wherein the memory cell retains the data state as long as the holding potential is applied.

56. The integrated circuit device of claim 54, wherein the body region functions as an inherent bipolar transistor.

57. The integrated circuit device of claim 54, wherein, when the body region is in a logic high data state, the holding potential causes bipolar current to flow in the body region.

58. The integrated circuit device of claim 57, wherein, when the body region is in a logic low data state, the holding potential prevents bipolar current from flowing in the body region.

59. The integrated circuit device of claim 54, wherein the holding potential includes a first potential applied to the gate and a second potential applied between the source region and the drain region.

60. The integrated circuit device of claim 59, wherein the first potential includes a voltage of approximately −

0.7 volts.

61. The integrated circuit device of claim 59, wherein the second potential includes a voltage approximately in a range of 2.2 volts to 2.6 volts.

62. The integrated circuit device of claim 59, wherein the second potential includes a voltage of approximately 2.3 volts.

63. The integrated circuit device of claim 59, wherein:

when the body region of the transistor is in a logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the body region and the second potential difference causes bipolar current to flow in the body region resulting from the increase of minority carriers in the body region due to impact ionization; and

when the body region of the transistor is in a logic low data state, the second potential is less than the threshold, wherein the flow of bipolar current is absent in the body region.

64. An integrated circuit device comprising:

a memory cell array including,

a plurality of word lines;

a plurality of source lines;

a plurality of bit lines; and

a plurality of memory cells arranged in a matrix of rows and columns;

wherein each memory cell includes a transistor comprising a body region configured to be electrically floating, a gate disposed over a first portion of the body region and coupled to an associated word line, a source region coupled to an associated source line, and a drain region coupled to an associated bit line;

wherein each memory cell is configured to hold a data state, wherein the data state includes a first data state representative of a first charge in the first portion of the body region, and a second data state representative of a second charge in the first portion of the body region; and

hold circuitry coupled to the memory cell array, the hold circuitry to continually apply a set of hold signals to the gate and between the source region and the drain region of the plurality of memory cells except for memory cells undergoing read operations and write operations, wherein the set of hold signals continually hold the data state of each of the plurality of memory cells by inherently refreshing the data state.

65. The integrated circuit device of claim 64, comprising data write circuitry coupled to the memory cell array.

66. The integrated circuit device of claim 64, wherein the data write circuitry is coupled to a first set of memory cells of the plurality of memory cells, the data write circuitry configured to apply first write control signals to the first set of memory cells during a write operation.

67. The integrated circuit device of claim 66, wherein the hold circuitry applies the set of hold signals to a second set of memory cells of the plurality of memory cells during the write operation, the second set of memory cells including the plurality of memory cells exclusive of the first set of memory cells.

68. The integrated circuit device of claim 64, comprising data sense circuitry coupled to the memory cell array and configured to sense the data state of the memory cells during a read operation, wherein, in response to read control signals applied to a third set of memory cells, the transistor of a memory cell generates a source current which is representative of the data state of the memory cell, wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the source current.

69. The integrated circuit device of claim 68, wherein the hold circuitry applies the set of hold signals to a fourth set of memory cells of the plurality of memory cells during the write operation, the fourth set of memory cells including the plurality of memory cells exclusive of the third set of memory cells.

70. The integrated circuit device of claim 64, wherein each memory cell of the memory cell array retains the data state as long as the set of hold signals is applied.

71. The integrated circuit device of claim 64, wherein, when the body region of each transistor is in the first data state, the holding potential causes bipolar current to flow in the body region as a result of impact ionization.

72. The integrated circuit device of claim 71, wherein, when the body region of each transistor is in the second data state, the holding potential prevents bipolar current from flowing in the body region.

73. The integrated circuit device of claim 64, wherein the set of hold signals includes a first potential applied to the gate and a second potential applied between the source region and the drain region of the transistor of at least one memory cell.

74. The integrated circuit device of claim 73, wherein the first potential includes a voltage of approximately −

0.7 volts.

75. The integrated circuit device of claim 73, wherein the second potential includes a voltage approximately in a range of 1.8 volts to 3.2 volts.

76. The integrated circuit device of claim 73, wherein the second potential includes a voltage of approximately 2.3 volts.