Bit stream conditioning circuit having adjustable input sensitivity

• US 8,014,471 B2
• Filed: 01/07/2008
• Issued: 09/06/2011
• Est. Priority Date: 07/22/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tonietto, Davide, Ghiasi, Ali
• Primary Examiner(s): Ha; Dac
• Assistant Examiner(s): DSOUZA, JOSEPH FRANCIS A
• Application Number:
  US11/970,191
• Publication Number:
  US 20080107424A1
• Time in Patent Office: 1,338 Days
• Field of Search: None
• US Class Current: 375/340
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10027 adjusting the signal strength during recording or reproduction, e.g. variable gain amplifiers optimum power control for optical discs G11B7/125
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: H04J 3/04 Distributors combined with modulators or demodulators pulse distributors in general H03K5/15; pulse counters H03K21/00 - H03K29/06; for telegraphy H04L5/22, H04L13/00 - H04L23/00, H04L25/45; for telephony H04Q11/04
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 1/205 jitter monitoring
• CPC Class Codes: H04L 2025/03401 PSK
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/20 Repeater circuits; Relay circuits

Abstract

A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Claims

1. A high-speed serial bit stream interface that communicatively couples a line side media type of a plurality of media types to a communication Application Specific Integrated Circuit (ASIC), the high-speed serial bit stream interface comprising:

a line side interface that communicatively couples to the line side media type, that receives a RX signal therefrom, and that transmits a TX signal thereto;

a board side interface that communicatively couples to the communication ASIC, that receives a TX signal therefrom, and that transmits the RX signal thereto;

a RX signal conditioning circuit communicatively coupled between a RX portion of the line side interface and a RX portion of the board side interface;

a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface;

a programmable control circuit coupled to the RX signal conditioning circuit and the TX signal conditioning circuit to cause the RX signal conditioning circuit and the TX signal conditioning circuit to perform signal conditioning on each of the RX signal and the TX signal, wherein the programmable control circuit operates to compensate for the line side media type of the plurality of media types;

wherein the RX signal conditioning circuit and the TX signal conditioning circuit each include;

a limiting amplifier that receives a respective serviced signal and that controllably amplifies the respective serviced signal to produce the respective serviced signal in a desired output range; and

a clock and data recovery circuit communicatively coupled to the output of the limiting amplifier, wherein the clock and data recovery circuit receives, recovers, and reclocks the respective serviced signal; and

wherein the limiting amplifier servicing the RX signal and the limiting amplifier servicing the TX signal are separately controlled by the programmable control circuit to produce the respective serviced signal in the desired output range.

2. The high-speed serial bit stream interface of claim 1, wherein the RX signal and the TX signal each comprise a single high-speed serial bit stream.

3. The high-speed serial bit stream interface of claim 1, wherein:

the limiting amplifier that services the TX signal as the respective serviced signal uses a first gain setting that is based upon the dynamic range of the TX signal that is coupled by the board side interface; and

the limiting amplifier that services the RX signal as the respective serviced signal uses a second gain setting that is based upon the dynamic range of the RX signal that is coupled by the line side interface.

4. The high-speed serial bit stream interface of claim 3, wherein:

the first gain setting is based upon output characteristics of the communication ASIC; and

the second gain setting is based upon the output characteristics of a communication device that produces the RX signal to the line side interface.

5. The high-speed serial bit stream interface of claim 4, wherein:

in a first configuration, the line side media type is a copper media type, and wherein the RX signal has a first dynamic range; and

in a second configuration, the line side media type is an optical media type, and wherein the RX signal has a second dynamic range, wherein the second dynamic range is less than the first dynamic range.

6. The high-speed serial bit stream interface of claim 1, wherein the RX signal conditioning circuit and the TX signal conditioning circuit each further comprise:

an output pre-emphasis circuit communicatively coupled to the output of the clock and data recovery circuit that controllably modifies the spectrum of the respective serviced signal to pre-compensate for spectral characteristics of a signal path upon which the respective serviced signal will be output.

7. The high-speed serial bit stream interface of claim 1, wherein the RX signal conditioning circuit and the TX signal conditioning circuit each further comprise:

an equalizer communicatively coupled to an input of the limiting amplifier that controllably spectrally shapes the respective serviced signal to compensate for spectral characteristics of a signal path from which the respective serviced signal was received.

8. The high-speed serial bit stream interface of claim 1, further comprising a Printed Circuit Board upon which the line side interface, the board side interface, the RX signal conditioning circuit, and the TX signal conditioning circuit are mounted.

9. The high-speed serial bit stream interface of claim 8, wherein the line side interface comprises a copper media connector.

10. The high-speed serial bit stream interface of claim 8, wherein the line side interface comprises a fiber optic media connector.