Wireless transceiver and method for use therewith

• US 8,014,723 B2
• Filed: 03/23/2007
• Issued: 09/06/2011
• Est. Priority Date: 03/23/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Dunn, William Franklin Jr., Worthy, Anna M., Batey, Charles Edward Jr., Henson, Matthew Brady
• Primary Examiner(s): Ghebretinsae; Temesgh
• Assistant Examiner(s): Tsvey; Gennadiy
• Application Number:
  US11/728,193
• Publication Number:
  US 20080232430A1
• Time in Patent Office: 1,628 Days
• Field of Search: 455/41.2, 375/354
• US Class Current: 455/41.2
• CPC Class Codes: H04B 1/3805 with built-in auxiliary receivers

Abstract

A wireless transceiver includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a wireless protocol, a processing module that executes the plurality of operational instructions, and a first interface module. The second integrated circuit includes a second interface module that couples data to and from the first interface module, an RF transceiver that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first interface module via the second interface module, and that generates data based on the second baseband signal to send to the first interface module via the second interface module.

Claims

1. An apparatus, comprising:

a long range transceiver;

a first short range transceiver; and

a second short range transceiver to communicate with a host device, the apparatus operable in a host-connected mode to function as an extended memory of the host device, and wherein the second short range transceiver comprises;

a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a Bluetooth protocol, a processing module that executes the plurality of operational instructions, and a first interface module; and

a second integrated circuit, wherein the second integrated circuit does not include a dedicated processor, wherein the second integrated circuit includes a second interface module that couples data to and from the first interface module, a radio frequency (RF) module that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first interface module via the second interface module, and that generates data based on the second baseband signal to send to the first interface module via the second interface module.

2. The apparatus of claim 1, wherein the first interface module operates in a master mode and the second interface module operates as a slave to the first interface module.

3. The apparatus of claim 1, wherein the plurality of protocol layers include a plurality of upper stack layers of the Bluetooth protocol and a plurality of lower stack layers of the Bluetooth protocol that are implemented on the first integrated circuit.

4. The apparatus of claim 1, wherein the first integrated circuit further comprises:

a direct memory access module that controls communication of data between the first integrated circuit and the second integrated circuit.

5. The apparatus of claim 1, wherein the first interface module and the second interface module communicate data via a serial communication path and wherein at least one of the first interface module and the second interface module include a synchronous receiver transmitter.

6. The apparatus of claim 1, wherein the first integrated circuit further includes:

an oscillator module for producing a clock signal;

wherein the first interface module couples the clock signal to the second interface module and wherein the baseband module and the RF module operate based on the clock signal.

7. The apparatus of claim 1, wherein the first integrated circuit further includes:

a DC to DC converter for producing a supply voltage;

wherein the first interface module couples the supply voltage to the second interface module and wherein the baseband module and the RF module operate based on the supply voltage.

8. The apparatus of claim 7, wherein the second integrated circuit generates at least one additional supply voltage based on the supply voltage.

9. The apparatus of claim 1, wherein at least a portion of the RF module and the baseband module are implemented using a state machine.

10. The apparatus of claim 1, wherein the memory module includes a random access memory.

11. The apparatus of claim 1, wherein the first integrated circuit further includes:

a memory interface for interfacing to an off-chip memory device.

12. The apparatus of claim 1, wherein the second integrated circuit further includes:

an oscillator module for producing a clock signal;

wherein the second interface module couples the clock signal to the first interface module and wherein the processing module operates based on the clock signal.

31. The apparatus of claim 1, integrated within a mobile communication device, and wherein the mobile communication device exits the host-connected mode in response to detecting a disconnection of the host device.

13. A wireless handset, comprising:

a long range transceiver to communicate with a long range wireless communication network;

a first short range transceiver to communicate with a short range wireless communication network; and

a second short range transceiver to communicate with a host device, the wireless handset operable in a host-connected mode to function as an extended memory of the host device, the second short range transceiver comprising;

a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a wireless protocol, a processing module that executes the plurality of operational instructions, and a first interface module; and

a second integrated circuit, wherein the second integrated circuit does not include a dedicated processor, wherein the second integrated circuit includes a second interface module that couples data to and from the first interface module, a radio frequency (RF) module that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first interface module via the second interface module, and that generates data based on the second baseband signal to send to the first interface module via the second interface module.

14. The wireless handset of claim 13, wherein the first integrated circuit further comprises:

a direct memory access module that controls communication of data between the first integrated circuit and the second integrated circuit.

15. The wireless handset of claim 13, wherein the first interface module and the second interface module communicate data between the first integrated circuit and the second integrated circuit via a serial communication path and wherein at least one of the first interface module and the second interface module include a synchronous receiver transmitter.

16. The wireless handset of claim 13, wherein the first integrated circuit further includes:

an oscillator module for producing a clock signal;

wherein the first interface module couples the clock signal to the second interface module and wherein the baseband module and the RF module operate based on the clock signal.

17. The wireless handset of claim 13, wherein the first integrated circuit further includes:

a DC to DC converter for producing a supply voltage;

wherein the first interface module couples the supply voltage to the second interface module and wherein the baseband module and the RF module operate based on the supply voltage.

18. The wireless handset of claim 17, wherein the second integrated circuit generates at least one additional supply voltage based on the supply voltage.

19. The wireless handset of claim 13, wherein at least a portion of the RF module and the baseband module are implemented using a state machine.

20. The wireless handset of claim 13, wherein the memory module includes a random access memory.

21. The wireless handset of claim 13, wherein the first integrated circuit further includes:

a memory interface for interfacing to an off-chip memory device.

22. The wireless handset of claim 13, wherein the first interface module operates in a master mode and the second interface module operates as a slave to the first interface module.

23. The wireless handset of claim 13, wherein the second integrated circuit further includes:

an oscillator module for producing a clock signal;

wherein the second interface module couples the clock signal to the first interface module and wherein the processing module operates based on the clock signal.

24. A method, comprising:

communicating with a long range wireless communication network via a long range transceiver at a mobile communication device;

communicating with a short range wireless communication network via a first short range transceiver at the mobile communication device;

communicating with a host device via a second short range transceiver at the mobile communication device, the mobile communication device operable in a host-connected mode to function as an extended memory of the host device, and wherein the second short range transceiver comprises;

a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a Bluetooth protocol, and a processing module that executes the plurality of operational instructions; and

bi-directionally communicating data between the first integrated circuit and a second integrated circuit, wherein the second integrated circuit does not include a dedicated processor, the second integrated circuit including a radio frequency (RF) module that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first integrated circuit, and that generates data based on the second baseband signal to send to the first integrated circuit.

25. The method of claim 24, wherein bi-directionally communicating the data includes controlling communication of the data between the first integrated circuit and the second integrated circuit via direct memory access.

26. The method of claim 24, wherein the data is communicated between the first integrated circuit and the second integrated circuit via a serial communication path.

27. The method of claim 24, further comprising:

generating a clock signal in the first integrated circuit; and

coupling the clock signal to the second integrated circuit, wherein the baseband module and the RF module operate based on the clock signal.

28. The method of claim 24, further comprising:

generating a supply voltage in the first integrated circuit; and

coupling the supply voltage to the second integrated circuit wherein the baseband module and the RF module operate based on the supply voltage.

29. The method of claim 28, further comprising:

generating an additional supply voltage in the second integrated circuit from the supply voltage.

30. The method of claim 24, wherein the first integrated circuit is configured to communicate with an off-chip memory device.

32. The method of claim 24, wherein the mobile communication device exits the host-connected mode in response to detecting a disconnection of the host device.