Electronic device with card interface

• US 8,015,338 B2
• Filed: 07/14/2010
• Issued: 09/06/2011
• Est. Priority Date: 03/08/2000
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suga, Masao, Okamoto, Kosei, Fujimoto, Akihisa, Sakamoto, Hiroyuki
• Primary Examiner(s): Cleary; Thomas J
• Application Number:
  US12/836,195
• Publication Number:
  US 20100281200A1
• Time in Patent Office: 419 Days
• Field of Search: 710/11, 710/14, 710/16, 710 62- 63, 710/105, 710301-302
• US Class Current: 710/301
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H05K 7/10 Plug-in assemblages of components , e.g. IC sockets

Abstract

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Claims

1. A memory system comprising:

connector pins including a plurality of data pins, a command pin, and a power signal pin, such that only one of the data pins is configured to receive data in a first operation mode, and the plurality of data pins are configured to receive data in a second operation mode;

a set of registers including a first register and a second register, the set of registers being connected to the connector pins; and

a controller which outputs the operation mode information to one of the connector pins in response to a first command, provides the operation voltage information to the command pin to transmit the operation voltage information in response to a second command, and sets the operation mode of the memory system into one of the first and second operation modes stored in the first register in response to a third command received via a command pin;

wherein the command pin is configured to receive the first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes;

one of the connector pins is configured to transmit the operation mode information in response to the first command;

the command pin is configured to receive the second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the memory system;

one of the connector pins is configured to transmit the operation voltage information in response to the second command;

the command pin is configured to receive the third command for setting an operation mode of the memory system into one of the first and second operation modes;

the first register storing own operation mode information of the memory system, the own operation mode information including bus width information which indicates one of the first and second operation modes such that, in the first operation mode, the system receives data using one of the data pins and, in the second mode, the system receives data using four of the data pins; and

the second register storing operation voltage information concerning an operation voltage of the memory system.

2. The memory system according to claim 1, wherein the command pin is configured to receive power voltage information concerning a power voltage, the power voltage being supplied externally via the power signal pin.

3. The memory system according to claim 2, wherein the command pin is configured to transmit a response if the memory system can operate with the power voltage.

4. The memory system according to claim 2, wherein the power signal pin is configured to receive an initial voltage before receiving the power voltage information.

5. The memory system according to claim 4, wherein the initial voltage differs from the power voltage.

6. The memory system according to claim 1, wherein

the command pin is configured to receive a fourth command for reading an address assigned to the memory system, and

the command pin is configured to transmit the address in response to the fourth command.

7. The memory system according to claim 6, wherein

the command pin is configured to receive a fifth command for selecting the memory system, the fifth command including an address indicating a storage device to be selected, and

the memory system is configured to shift the memory system to a selected state if the address included in the fifth command is identical to the address assigned to the memory system.

8. The system according to claim 1, wherein

the command pin is configured to receive a sixth command for reading identification data, unique to the memory system, from an electronic device, and

the command pin is configured to transmit the identification data in response to the sixth command.

9. The memory system according to claim 8, wherein the system is configured to shift the system from a Ready State to an Identification State after transmitting the identification data.

10. The memory system according to claim 1, further comprising a memory core being connected to the set of registers.

11. The memory system according to claim 1, wherein the controller is configured to receive power voltage information concerning a power voltage, the power voltage supplied via the power signal pin.

12. The memory system according to claim 11, wherein the controller is configured to transmit a response if the system can operate with the power voltage.

13. The memory system according to claim 11, wherein the controller is configured to receive an initial voltage via the power signal pin before receiving the power voltage information.

14. The memory system according to claim 13, wherein the initial voltage differs from the power voltage.

15. The system according to claim 1, wherein the controller is configured to receive a seventh command for reading an address, assigned to the system via the command pin, and

wherein the controller is configured to transmit the address via the command pin in response to the seventh command.

16. The memory system according to claim 15, wherein the controller is configured to receive an eighth command for selecting the system, the eighth command including an address indicating portion of the system to be selected;

and

wherein the controller is configured to shift the system to a selected state if the address included in the eighth command is identical to the address assigned to the system.

17. The memory system according to claim 1, wherein the controller is configured to receive a ninth command for reading identification data, unique to the system via the command pin;

and

wherein the controller is configured to transmit the identification data via the command pin in response to the ninth command.

18. The memory system according to claim 17, wherein the controller is configured to shift the system from a ready state to an identification state after transmitting the identification data.