Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device

• US 8,015,348 B2
• Filed: 12/29/2010
• Issued: 09/06/2011
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Nguyen, David, Shen, Ming-Shiang, Lee, Charles C., Ma, Abraham Chih-Kang, Yu, I-Kang
• Primary Examiner(s): Yu; Jae U
• Application Number:
  US12/980,591
• Publication Number:
  US 20110093653A1
• Time in Patent Office: 251 Days
• Field of Search: 711/103, 711/202, 711/203, 711/206, 714/8
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: H01R 13/447 Shutter or cover plate
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 1/182 associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: H05K 2201/10189 Non-printed connector
• CPC Class Codes: H05K 2201/10446 Mounted on an edge soldering edge mounted components H05K3/3405; edge terminals H05K2201/1034
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 5/0278 of USB type details relating to connectors H01R27/00

Abstract

Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Claims

1. A system for managing memory address of a multi-level cell (MLC) based flash memory device comprising:

an input/output interface circuit, coupling to a processing unit, configured for receiving a logical sector address (LSA) along with a data transfer request from a host computing device, said processing unit is configured for extracting set, entry, page and sector numbers from the LSA using an indexing scheme, said processing unit further comprising a page buffer, an address correlation page usage memory (ACPUM), a partial logical-to-physical address and page usage information (PLTPPUI) tracking table, a wear leveling counter and bad block indicator (WL/BB) tracking table; and

a flash memory that includes a reserved area for a plurality of first physical blocks and a plurality of second physical blocks, the first physical blocks being referenced by a plurality of respective first special logical addresses and the second physical blocks by a plurality of respective second special logical addresses;

wherein the first physical blocks are configured for storing PLTPPUI and the second physical blocks for storing wear leveling and bad block (WL/BB) indicator, said ACPUM is configured to keep one set, corresponding to the set number, of PLTPPUI, the PLTPPUI tracking table is configured to hold a correlation between the first special logical addresses and the first physical blocks and the WL/BB tracking table is configured to hold a correlation between the second special logical addresses and the second physical blocks.

2. The system of claim 1, wherein the ACPUM comprises a plurality of entries with each entry corresponding to a physical block number and a set of page usage information, the set of page usage information is configured for respective pages of said physical block.

3. The system of claim 1, wherein the page buffer is configured to hold data sectors retrieved from the flash memory when the data transfer request is a data write request.

4. The system of claim 1, wherein the page buffer is configured to hold received data sector from the host computing device when the data transfer request is a data read request.

5. The system of claim 1, wherein the ACPUM'"'"'s contents are written to at least one of the first physical blocks one page at a time under MLC data programming rules which include (a) writing to a higher page number sequentially in a same one of the first physical blocks and (b) each page can only be written once thereby a new blank one of the first physical blocks is required for writing to a page with same page number in second time.

6. The system of claim 5, wherein each of the first physical blocks in the reserved area is referenced by one of a plurality of first special logical addresses and a correlation between the first physical blocks and the first special logical addresses is kept in a PLTPPUI tracking table.

7. The system of claim 6, wherein the PLTPPUI tracking table further contains a tracking number and a highest page number for said each of the first physical blocks, the tracking number is configured for identifying which version of a particular set of PLTPPUI is stored in said each of the first physical blocks and the highest page is configured for tracking which page has been written in said each of the first physical blocks.

8. The system of claim 7, wherein the tracking number associated with particular one of the first special logical addresses are written to spare area of first page of said each of the first physical blocks in the reserved area of the flash memory.

9. The system of claim 8, wherein the PLTPPUI tracking table is rebuilt in each initialization of the MLC flash memory device from stored tracking number and stored first special logical address in the spare area of the first page of said each of the first physical blocks in the reserved area of the flash memory.

10. The system of claim 1, wherein the indexing scheme comprises the PLTPPUI and is based on physical characteristics of the flash memory including total number of sets, entries, pages and sectors, and ratios among said sets, said entries, said pages and said sectors.

11. The system of claim 1, wherein the reserved area of the flash memory is defined by an initial manufacturing program from the MLC based flash memory device'"'"'s manufacturer.