Wake-and-go mechanism with exclusive system bus response

• US 8,015,379 B2
• Filed: 02/01/2008
• Issued: 09/06/2011
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US12/024,250
• Publication Number:
  US 20100293341A1
• Time in Patent Office: 1,313 Days
• Field of Search: 711/137, 711/152, 711/154, 711/146, 711/163, 711/E12.001, 712/207, 712/216
• US Class Current: 711/163
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity and determines whether the wake-and-go engine obtains a lock for the target address. Responsive to obtaining the lock for the target address, the wake-and-go engine holds the lock for the thread.

Claims

1. A method, in a data processing system, for performing a look-ahead operation in a wake-and-go mechanism, the method comprising:

responsive to detecting instructions indicating that a thread is waiting for data at a target address, issuing, by the wake-and-go mechanism, a look-ahead load command on a system bus to read a data value from the target address;

performing, by the wake-and-go mechanism, a comparison operation to determine whether the data value at the target address indicates that the data for which the thread is waiting is at the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is not at the target address, populating a wake-and-go storage array with the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is at the target address, issuing, by the wake-and-go mechanism, a load command on the system bus to read the data value from the target address with data exclusivity; and

responsive to the wake-and-go mechanism obtaining the lock for the target address, holding, by the wake-and-go mechanism, the lock for the thread.

2. The method of claim 1, wherein the look-ahead load command is a load without reservation command.

3. The method of claim 1, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

4. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

5. The method of claim 4, wherein responsive to detecting a data access at the target address on the system bus, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

6. The method of claim 1, wherein the wake-and-go mechanism determines that the data for which the thread is waiting is at the target address responsive to a direct memory access operation that moves data from a source address to the target address.

7. The method of claim 1, wherein issuing a load command on the system bus to read the data value from the target address with data exclusivity comprises issuing a load with reservation command on the system bus.

8. The method of claim 1, further comprising:

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, placing an entry in the wake-and-go storage array to spin on the lock for the target address.

9. A data processing system, comprising:

a wake-and-go mechanism; and

a wake-and-go storage array,

wherein the wake-and-go mechanism is configured to;

responsive to detecting instructions indicating that a thread is waiting for data at a target address, issue a look-ahead load command on a system bus to read a data value from a target address;

perform a comparison operation to determine whether the data value at the target address indicates that the data for which the thread is waiting is at the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is not at the target address, populate the wake-and-go storage array with the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is at the target address, issue a load command on the system bus to read the data value from the target address with data exclusivity; and

responsive to the wake-and-go mechanism obtaining the lock for the target address, hold the lock for the thread.

10. The data processing system of claim 9, wherein the look-ahead load command is a load without reservation operation.

11. The data processing system of claim 9, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

12. The data processing system of claim 9, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

13. The data processing system of claim 12, wherein responsive to detecting a data access at the target address on the system bus, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

14. The data processing system of claim 9, wherein the wake-and-go mechanism determines that the data for which the thread is waiting is at the target address responsive to a direct memory access operation that moves data from a source address to the target address.

15. The data processing system of claim 9, wherein issuing a load command on the system bus to read the data value from the target address with data exclusivity comprises issuing a load with reservation command on the system bus.

16. The data processing system of claim 9, wherein the wake-and-go mechanism is further configured to:

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, place an entry in the wake-and-go storage array to spin on the lock for the target address.

17. A computer program product comprising a computer useable storage medium having a computer readable program stored thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

issue, by the wake-and-go mechanism, a look-ahead load command on a system bus to read a data value from a target address;

perform a comparison operation to determine whether the data value at the target address indicates that the data for which the thread is waiting is at the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is not at the target address, populate a wake-and-go storage array with the target address;

in response to the comparison resulting in a determination that the data for which the thread is waiting is at the target address, issue, by the wake-and-go mechanism, a load command on the system bus to read the data value from the target address with data exclusivity; and

responsive to the wake-and-go mechanism obtaining the lock for the target address, hold, by the wake-and-go mechanism, the lock for the thread.

18. The computer program product of claim 17, wherein the look-ahead load command is a load without reservation operation.

19. The computer program product of claim 17, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

20. The computer program product of claim 17, wherein the computer readable program further causes the computing device to:

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, place an entry in the wake-and-go storage array to spin on the lock for the target address.