Configurable memory manager

• US 8,015,386 B1
• Filed: 03/31/2008
• Issued: 09/06/2011
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kulkarni, Chidamber R., Brebner, Gordon J.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/059,161
• Time in Patent Office: 1,254 Days
• Field of Search: 711/202, 711/203, 711/170, 711/E12.002, 710/22, 710/26
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0653 with centralised address assignment

Abstract

A configurable memory manager is configurable with various configuration parameters. The configurable memory manager has client ports for receiving requests for accessing memories and memory ports for accessing respective memories. The client and memory ports are each independently configurable to specify the parameter of a data width of the port. The configurable memory manager includes a switch and a translator. The translator translates a virtual address in each of the requests into an identifier of one of the memories and a physical address in the memory. The switch transfers each request from the client port receiving the request to the memory port for accessing the memory identified by the identifier for the virtual address in the request.

Claims

1. A configurable memory manager, comprising:

a first plurality of ports, each port of the first plurality arranged to receive requests for accessing a plurality of memories, and each port of the first plurality being independently configurable to specify one of a first plurality of data widths of the port;

a second plurality of ports, each port of the second plurality arranged to access a respective one of the memories, each port of the second plurality being independently configurable to specify one of a second plurality of data widths of the port;

a translator configured to translate a virtual address of each of the requests into an identifier of one of the memories and a physical address in the memory;

wherein the translator is configurable to associate each port of the second plurality with any one of a plurality of translation look-aside buffers, each translation look-aside buffer configured to translate the virtual address of each request into the physical address for the associated port; and

a switch coupled to the translator and to the first and second pluralities of ports, the switch, responsive to the identifier translated from a request received at a port of the first plurality, arranged to transfer the physical address translated from the request to a port of the second plurality for accessing the memory identified by the identifier.

2. The configurable memory manager of claim 1, wherein two ports of the first plurality are configurable to specify respective data widths for the two ports that are a same one or different ones of the first plurality of data widths.

3. The configurable memory manager of claim 1, wherein two ports of the second plurality are configurable to specify respective data widths for the two ports that are a same one or different ones of the second plurality of data widths.

4. The configurable memory manager of claim 1, wherein each port of the first and second pluralities is independently configurable to specify the data width of the port and a number of successive data transfers of the requests for the port.

5. The configurable memory manager of claim 1, wherein the translator includes a content addressable memory that is configurable to associate the identifier with a plurality of ranges of the virtual address of the requests.

6. The configurable memory manager of claim 1, wherein the translator includes a content addressable memory that is configurable to associate each of the plurality of translation look-aside buffers with a respective plurality of ranges of the virtual address of the requests.

7. The configurable memory manager of claim 1, wherein the translator is dynamically configurable, while the configurable memory manager is processing at least one of the requests, to change an association of the identifier of one of the memories from one to another of the plurality of translation look-aside buffers for translating the virtual address of the requests into the physical address.

8. The configurable memory manager of claim 1, wherein the switch is configurable to select an arbitration protocol for ordering acceptance of the requests among the first plurality of ports.

9. The configurable memory manager of claim 8, wherein the switch includes a request arbiter that implements at least two arbitration protocols from round robin, time domain multiple access, priority for the first plurality of ports, weighted priority for the first plurality of ports, and rate based scheduling, and the request arbiter is configurable to select the arbitration protocol from the at least two arbitration protocols.

10. The configurable memory manager of claim 1, wherein the switch is configurable to select an arbitration protocol for ordering acceptance among the second plurality of ports of a plurality of responses from the memories to the requests.

11. The configurable memory manager of claim 1, further comprising a configuration port arranged for configuration of the first and second pluralities of ports, the translator, and the switch.

12. The configurable memory manager of claim 1, further comprising a configuration port arranged for configuration of a page table for translating the virtual address of each of the requests into the physical address in the memory identified by the identifier.

13. The configurable memory manager of claim 1, further comprising a configuration port arranged for configuration of one of the translation look-aside buffers of the translator with a width of the virtual addresses of the requests received at a port of the first plurality.

14. The configurable memory manager of claim 1, wherein the translator includes a block memory for storing each translation look-aside buffer, and the translation look-aside buffer having a respective entry for each of a plurality of virtual pages included in the virtual address of recently received ones of the requests, the respective entry including a physical page of the physical address, the physical page associated with the virtual page in a table of the virtual pages.

15. The configurable memory manager of claim 1, wherein the translator includes a block memory for storing each translation look-aside buffer, and the translation look-aside buffer having a respective entry for each of a plurality of virtual pages included in the virtual address of recently received ones of the requests, the respective entry including a protection specifying permitted access by the requests having the virtual address that includes the virtual page, the protection specifying the permitted access that is at least one of read access and write access.

16. The configurable memory manager of claim 1, wherein the translator includes a block memory for storing each translation look-aside buffer, and the translation look-aside buffer having a respective entry for each of a plurality of virtual pages included in the virtual address of recently received ones of the requests, the respective entry including a least-recently-used flag and a dirty flag, the least-recently used flag indicating the virtual page is not included in the virtual addresses of more recently received ones of the requests, and the dirty flag indicating the requests include a write request that has the virtual page included in the virtual address of the write request.

17. The configurable memory manager of claim 1, wherein the switch transfers the request that is a read request from the port of the first plurality receiving the read request to the port of the second plurality for the memory of the identifier for the virtual address of the read request and transfers read data for the read request at the physical address in the memory from the port of the second plurality to the port of the first plurality, and the switch transfers the request that is a write request and includes write data from the port of the first plurality receiving the write request to the port of the second plurality for the memory of the identifier for the virtual address of the write request.

18. The configurable memory manager of claim 1, wherein the configurable memory manager is included within a programmable logic device that also includes configurable logic and interconnect resources, and the first and second pluralities of ports are coupled to the configurable interconnect resources of the programmable logic device.

19. The configurable memory manager of claim 18, wherein the programmable logic device further includes at least one block memory for storing a page table for translating the virtual address of each of the requests into the physical address in the memory identified by the identifier.