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Decompressors for low power decompression of test patterns

  • US 8,015,461 B2
  • Filed: 12/17/2009
  • Issued: 09/06/2011
  • Est. Priority Date: 07/21/2006
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • inputting compressed test pattern bits;

    generating decompressed test pattern bits from the compressed test pattern bits;

    storing the decompressed test pattern bits in one or more registers; and

    loading scan chains of a circuit-under-test with the decompressed test pattern bits stored in the one or more registers, the loading being performed for two or more scan chain shift cycles such that the decompressed test pattern bits stored in the one or more registers are repeatedly loaded into the scan chain.

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