Color filter array alignment mark formation in backside illuminated image sensors

• US 8,017,426 B2
• Filed: 07/09/2008
• Issued: 09/13/2011
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Brady, Frederick T.
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US12/169,709
• Publication Number:
  US 20100006909A1
• Time in Patent Office: 1,161 Days
• Field of Search: 438/70, 438/72, 438/401, 438/417, 438/489, 257/E31.127
• US Class Current: 438/70
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements

Abstract

A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Claims

1. A method of forming color filter array alignment marks in an image sensor wafer, the image sensor wafer being utilized to form a plurality of image sensors each having a pixel array configured for backside illumination, the image sensor wafer comprising at least a substrate and a sensor layer, the method comprising:

forming color filter array alignment mark openings in the sensor layer; and

forming a single crystalline silicon epitaxial layer on unetched portions of a frontside surface of the sensor layer while simultaneously forming

polysilicon color filter array alignment marks in respective ones of the etched color filter array alignment mark openings in the sensor layer.

2. The method of claim 1 wherein the image sensor wafer comprises an oxide layer arranged between the substrate and the sensor layer, the method further comprising:

exposing a backside surface of the oxide layer; and

forming color filter arrays on the backside surface of the oxide layer in alignment with the color filter array alignment marks.

3. The method of claim 2 wherein exposing a backside surface of the oxide layer further comprises:

forming a dielectric layer on a frontside surface of the epitaxial layer;

attaching a handle wafer to a frontside surface of the dielectric layer; and

removing the substrate to expose the backside surface of the oxide layer.

4. The method of claim 3 further comprising separating a resulting processed wafer into the plurality of image sensors.

5. The method of claim 1 wherein forming color filter array alignment mark openings in the sensor layer further comprises etching the openings such that the openings terminate in the sensor layer.

6. The method of claim 2 wherein forming color filter array alignment mark openings in the sensor layer further comprises etching the openings such that the openings extend through the sensor layer and terminate in the oxide layer.

7. The method of claim 2 wherein forming color filter array alignment mark openings in the sensor layer further comprises etching the openings such that the openings extend through the sensor layer and terminate at a frontside surface of the oxide layer.

8. The method of claim 2 further comprising forming microlenses over respective color filter elements of the color filter arrays in alignment with the color filter array alignment marks.

9. The method of claim 3 wherein said dielectric layer comprises an interlayer dielectric and further comprises an intermetal dielectric separating multiple levels of metallization.

10. The method of claim 1 wherein the image sensor wafer comprises a silicon-on-insulator (SOI) wafer.