Optically transparent wires for secure circuits and methods of making same

• US 8,017,514 B2
• Filed: 05/05/2008
• Issued: 09/13/2011
• Est. Priority Date: 05/05/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ayotte, Stephen Peter, Sullivan, Timothy Dooling, Gambino, Jeffrey Peter, Watson, Kimball M.
• Primary Examiner(s): Stark; Jarrett J
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/115,056
• Publication Number:
  US 20090273084A1
• Time in Patent Office: 1,226 Days
• Field of Search: 257/749, 438/4, 438/7, 438/16, 438/609
• US Class Current: 438/609
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Claims

1. A method, comprising:

(a) forming a dielectric layer on an integrated circuit substrate, said substrate including semiconductor devices, said dielectric layer having a bottom surface closet from said substrate and an opposite top surface furthest to said substrate;

(b) forming electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer; and

(c) forming an electrically conductive and patterned third wire on said top surface of said dielectric layer and on said top surfaces of said first and second wires, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy.

2. The method of claim 1, wherein (c) includes:

forming an electrically conductive layer on said top surface of said dielectric layer and over said top surfaces of said first and second wires;

forming an additional dielectric layer on a top surface of said conductive layer; and

photolithographically patterning said additional dielectric layer and said electrically conductive layer to form said third wire and a dielectric cap on a top surface of said third wire.

3. The method of claim 1, wherein said third wire abuts said top surface of said first wire and said top surface of said second wire.

4. The method of claim 1, further including:

between (b) and (c), either (i) forming an electrically conductive first diffusion barrier layer on said top surface of said first wire and an electrically conductive second diffusion barrier layer on said top surface of said second wire, or (ii) forming a first recess in said first wire and a second recess in said second wire and backfilling said first recess with said first diffusion barrier layer and backfilling said second recess with said second diffusion barrier layer; and

wherein said third wire abuts top surfaces of said first and second diffusion barrier layers.

5. The method of claim 1, wherein a combination of a material of said third wire and a thickness of said third wire render said third wire transparent to light having a wavelength between about 400 nm and about 700 nm.

6. The method of claim 1, wherein said third wire has a thickness of between about 2 nm and about 10 nm.

7. The method of claim 1, wherein (i) said third wire comprises a material selected from the group consisting of aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, chromium and combinations thereof and (ii) each said first and second wires include copper.

8. A method, comprising:

(a) forming a dielectric layer on an integrated circuit substrate, said substrate including semiconductor devices, said substrate including semiconductor devices, said dielectric layer having a bottom surface closet to said substrate and an opposite top surface furthest from said substrate;

(b) forming electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer; and

(c) forming an electrically conductive and patterned third wire, said third wire formed in said dielectric layer, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy.

9. The method of claim 8, wherein (c) includes:

forming a dielectric masking layer on said top surface of said dielectric layer and over said top surfaces of said first and second wires;

forming a patterned photoresist layer on said dielectric layer, regions of said first and second wires and a region of said dielectric layer not covered by said patterned photoresist layer;

ion implanting a metallic species into said dielectric layer and regions of said first and second wires not covered by said patterned photoresist layer; and

removing said patterned photoresist layer.

10. The method of claim 8, wherein said third wire abuts said first wire and said second wire.

11. The method of claim 8, further including:

between (b) and (c), either (i) forming an electrically conductive first diffusion barrier layer on said top surface of said first wire and an electrically conductive second diffusion barrier layer on said top surface of said second wire, or (ii) forming a first recess in said first wire and a second recess in said second wire and backfilling said first recess with said first diffusion barrier layer and backfilling said second recess with said second diffusion barrier layer; and

wherein said third wire abuts said first and second diffusion barrier layers.

12. The method of claim 8, wherein a combination of a material of said third wire and a thickness of said third wire render said third wire transparent to light having a wavelength between about 400 nm and about 700 nm.

13. The method of claim 8, wherein said third wire has a thickness of between about 2 nm and about 10 nm.

14. The method of claim 8, wherein (i) said third wire comprises a material selected from the group consisting of tungsten, titanium, copper and combinations thereof and (ii) each of said first and second wires include copper.