Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief

• US 8,017,515 B2
• Filed: 12/10/2008
• Issued: 09/13/2011
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Marimuthu, Pandi C., Suthiwongsunthorn, Nathapong, Huang, Shuangwu
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US12/332,325
• Publication Number:
  US 20100140752A1
• Time in Patent Office: 1,007 Days
• Field of Search: 257/737, 257/738, 257/E23.021, 257/E23.069, 257/734, 257/735, 257/750, 257/758, 257780-784, 438/612, 438/613, 438/614
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4823 : connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over a top surface of the substrate;

forming a first insulating layer over the substrate;

forming a first conformal dielectric layer over the first insulating layer;

forming a second conductive layer over the first conductive layer and first conformal dielectric layer;

forming a second conformal dielectric layer over the second conductive layer;

depositing a compliant polymer material over the second conformal dielectric layer and second conductive layer;

forming a third conductive layer over the compliant polymer material and second conductive layer, the third conductive layer being electrically connected to the second conductive layer; and

forming a first solder bump over the third conductive layer.

2. The method of claim 1, further including removing a portion of the compliant polymer material over the second conformal dielectric layer.

3. The method of claim 1, further including forming a conductive via through a back surface of the substrate, opposite the top surface of the substrate, the conductive via being electrically connected to the first conductive layer.

4. The method of claim 3, wherein the conductive via has vertical or tapered sidewalls.

5. The method of claim 3, further including forming a second solder bump over the conductive via.

6. The method of claim 3, further including:

forming a fourth conductive layer over the back surface of the substrate and into the conductive via, the fourth conductive layer being electrically connected to the first conductive layer;

forming a second insulating layer over the fourth conductive layer;

removing a portion of the second insulating layer to expose the fourth conductive layer; and

forming a second solder bump over the fourth conductive layer.

7. The method of claim 1, wherein the compliant polymer material has a coefficient of thermal expansion (CTE) which is less than CTE of the second conformal dielectric layer, second conductive layer, and third conductive layer.

8. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over a top surface of the substrate;

forming a first insulating layer over the substrate;

forming a first dielectric layer over the first insulating layer;

forming a second conductive layer over the first conductive layer and first dielectric layer;

forming a second dielectric layer over the second conductive layer;

depositing a polymer material over the second dielectric layer and second conductive layer; and

forming a third conductive layer over the polymer material and second conductive layer, the third conductive layer being electrically connected to the second conductive layer.

9. The method of claim 8, further including forming a solder bump over the third conductive layer.

10. The method of claim 8, further including removing a portion of the polymer material over the second conformal dielectric layer.

11. The method of claim 8, further including forming a conductive via through a back surface of the substrate, opposite the top surface of the substrate, the conductive via being electrically connected to the first conductive layer.

12. The method of claim 11, wherein the conductive via has vertical or tapered sidewalls.

13. The method of claim 11, further including forming a solder bump over the conductive via.

14. The method of claim 11, further including:

forming a fourth conductive layer over the back surface of the substrate and into the conductive via, the fourth conductive layer being electrically connected to the first conductive layer; and

forming a second insulating layer over the fourth conductive layer;

removing a portion of the second insulating layer to expose the fourth conductive layer; and

forming a solder bump over the fourth conductive layer.

15. The method of claim 8, wherein the polymer material has a coefficient of thermal expansion (CTE) which is less than CTE of the second dielectric layer, second conductive layer, and third conductive layer.

16. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over a top surface of the substrate;

forming a first insulating layer over the substrate;

forming a second conductive layer over the first conductive layer and first insulating layer;

depositing a polymer material over the second conductive layer;

forming a third conductive layer over the second conductive layer, the third conductive layer being electrically connected to the second conductive layer;

forming a first dielectric layer over the first insulating layer; and

forming a second dielectric layer over the second conductive layer.

17. The method of claim 16, wherein the polymer material has a coefficient of thermal expansion (CTE) which is less than CTE of the second dielectric layer, second conductive layer, and third conductive layer.

18. The method of claim 16, further including forming a conductive via through a back surface of the substrate, opposite the top surface of the substrate, the conductive via being electrically connected to the first conductive layer.

19. The method of claim 18, wherein the conductive via has vertical or tapered sidewalls.

20. A semiconductor device, comprising:

a substrate;

a first conductive layer formed over a top surface of the substrate;

a first insulating layer formed over the substrate;

a first dielectric layer formed over the first insulating layer;

a second conductive layer formed over the first conductive layer and first dielectric layer;

a second dielectric layer formed over the second conductive layer;

a polymer material deposited over the second dielectric layer and second conductive layer; and

a third conductive layer formed over the polymer material and second conductive layer, the third conductive layer being electrically connected to the second conductive layer.

21. The semiconductor device of claim 20, further including a conductive via formed through a back surface of the substrate, opposite the top surface of the substrate, the conductive via being electrically connected to the first conductive layer.

22. The semiconductor device of claim 21, wherein the conductive via has vertical or tapered sidewalls.

23. The semiconductor device of claim 21, further including:

a fourth conductive layer formed over the back surface of the substrate and into the conductive via, the fourth conductive layer being electrically connected to the first conductive layer;

a second insulating layer formed over the fourth conductive layer; and

a second solder bump formed over the fourth conductive layer.

24. The semiconductor device of claim 20, wherein the polymer material has a coefficient of thermal expansion (CTE) which is less than CTE of the second dielectric layer, second conductive layer, and third conductive layer.