Nonvolatile memory cell comprising a reduced height vertical diode
First Claim
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1. A nonvolatile memory cell comprising:
- a rail-shaped first conductor formed at a first height above a substrate;
a rail-shaped second conductor formed above the first conductor; and
a vertically oriented first pillar comprising a p-i-n first diode,wherein the first pillar is disposed between the second conductor and the first conductor;
wherein the first diode comprises an intrinsic or lightly doped region, and wherein the first diode has a height between about 500 angstroms and about 3000 angstroms; and
wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater.
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Abstract
A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
64 Citations
46 Claims
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1. A nonvolatile memory cell comprising:
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a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode, wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region, and wherein the first diode has a height between about 500 angstroms and about 3000 angstroms; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A monolithic three dimensional memory array comprising:
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i) a first memory level, the first memory level comprising; a) a plurality of substantially parallel, substantially coplanar first conductors formed above a substrate; b) a plurality of substantially parallel, substantially coplanar second conductors formed above the first conductors; and c) a plurality of vertically oriented first junction diodes; wherein each first junction diode is disposed between one of the plurality of substantially parallel, substantially coplanar first conductors and one of the plurality of substantially parallel, substantially coplanar second conductors; wherein the first junction diodes have a first height between about 500 angstroms and about 3000 angstroms; and ii) at least a second memory level monolithically formed on the first memory level. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification