Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate

• US 8,018,072 B1
• Filed: 12/23/2008
• Issued: 09/13/2011
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Lim, Jui Min, Miks, Jeffrey A.
• Primary Examiner(s): Williams; A
• Application Number:
  US12/342,386
• Time in Patent Office: 994 Days
• Field of Search: 257/777, 257/723, 257/686, 257/685, 257/712, 257/675, 257/710, 257/704, 257/680, 257/730, 257/774, 257/773, 257/676, 257/713, 257/727, 257/720, 257/707, 257/706, 257/691, 257/787, 257/796, 257/684, 257/718, 257/778, 257/719, 257/667, 257/E23.092
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16151 Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16315 Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.

Claims

1. A semiconductor device comprising:

a substrate;

a die attached to a first surface of the substrate;

a heat sink having an approximately planer member and support members extending from the planer member, the support members attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die;

an encapsulant for encapsulating the device, wherein an entire exterior surface of the planer member is exposed; and

a non-tapered opening formed in the planer member, the encapsulant injected through the opening to encapsulate the cavity, the encapsulant partially filling the non-tapered opening.

2. The semiconductor device in accordance with claim 1 further comprising:

a filler die having a first surface attached to the interior surface of the planer member and a second surface attached to a first surface of the die; and

at least one channel formed in the first surface of the filler die, the channel aligned with the non-tapered opening.

3. The semiconductor device in accordance with claim 2 further comprising a thermal interface material applied between the first surface of the filler die and the interior surface of the planer member and between the second surface of the filler die and the first surface of the die.

4. The semiconductor device in accordance with claim 2 further comprising a plurality of channels formed in the first surface of the filler die, the plurality of channels having an intersection, the intersection aligned with the non-tapered opening.

5. The semiconductor device in accordance with claim 2 wherein the filler die has an approximately equal Coefficient of Thermal Expansion (CTE) as the die.

6. The semiconductor device in accordance with claim 1 further comprising a plurality of contacts coupled to a second surface of the substrate.

7. The semiconductor device in accordance with claim 2 further comprising a plurality of contacts coupled to a second surface of the substrate.

8. The semiconductor device in accordance with claim 1 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the non-tapered opening.

9. The semiconductor device in accordance with claim 8 further comprising a thermal interface material applied between the first surfaces of the filler dies and the interior surface of the planer member and between the second surfaces of the filler dies and the first surface of the die.

10. The semiconductor device in accordance with claim 1 further comprising a plurality of filler dies having first surface attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form a plurality of pathway in the first surface of the die, the plurality of pathways having an intersection, the intersection of the pathways aligned with the non-tapered opening.

11. The semiconductor device in accordance with claim 8 further comprising a plurality of contacts coupled to a second surface of the substrate.

12. A semiconductor device comprising:

a substrate;

a die attached to a first surface of the substrate;

a heat sink having an approximately planer member and support members extending from the planer member, the support members attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die;

an encapsulant for encapsulating the device, wherein an exterior surface of the planer member is exposed;

means formed in the planer member for injecting the encapsulant into the cavity, the encapsulant partially filling the means;

a filler die having a first surface attached to the interior surface of the planer member and a second surface attached to a first surface of the die; and

means formed in the first surface of the filler die for allowing the encapsulant to flow across the first surface of filler die, the means formed in the first surface of the filler die aligned with the means formed in the planer member.

13. The semiconductor device in accordance with claim 12 further comprising means placed between the second surface of the filler die and the first surface of the die and the first surface of the filler die and the interior surface of the planer member to increase thermal transfer efficiency.

14. The semiconductor device in accordance with claim 12 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the means formed in the planer member.

15. The semiconductor device in accordance with claim 14 further comprising means applied between the first surfaces of the filler dies and the interior surface of the planer member and between the second surfaces of the filler dies and the first surface of the die to increase thermal transfer efficiency.

16. A semiconductor device comprising:

a substrate;

a die attached to a first surface of the substrate;

a heat sink positioned over the die and attached to the first surface of the substrate to form a cavity over the die;

an encapsulant for encapsulating the device, wherein an exterior surface of the planer member is exposed;

a non-tapered opening formed in the planer member, the encapsulant injected through the opening to encapsulate the cavity, the encapsulant partially filling the non-tapered opening;

a filler die having a first surface attached to an interior surface of the heat sink and a second surface attached to a first surface of the die; and

at least one channel formed in the first surface of the filler die, the channel aligned with the non-tapered opening.

17. The semiconductor device in accordance with claim 16 further comprising a plurality of channels formed in the first surface of the filler die, the plurality of channels having an intersection, the intersection aligned with the non-tapered opening.

18. The semiconductor device in accordance with claim 16 further comprising a plurality of filler dies having first surfaces attached to the interior surface of the planer member and second surfaces attached to a first surface of the die, the plurality of filler dies positioned on the first surface of the die to form at least one pathway in the first surface of the die, the pathway aligned with the non-tapered opening.