Buck-boost regulator

• US 8,018,212 B1
• Filed: 06/06/2008
• Issued: 09/13/2011
• Est. Priority Date: 08/24/2007
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Petricek, Shea Lynn
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US12/134,800
• Time in Patent Office: 1,194 Days
• Field of Search: 323/247, 323/259, 323/265, 323/273, 323/282, 323/328, 323/344
• US Class Current: 323/259
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

A buck-boost regulator for converting an input voltage to an output voltage which includes an inductor, an error circuit providing an error voltage, buck and boost switching circuits, buck and boost ripple circuits, and buck and boost hysteretic comparator circuits. The buck switching circuit switches a first end of the inductor, the buck ripple circuit replicates ripple current through the inductor based on the buck pulse signal and provides a buck ripple voltage, and the buck hysteretic comparator circuit develops the buck pulse signal based on a buck window voltage range using the error voltage. The boost switching circuit switches a second end of the inductor, the boost ripple circuit replicates ripple current through the inductor based on the boost pulse signal and provides a boost ripple voltage, and the boost hysteretic comparator circuit develops the boost pulse signal based on a boost window voltage range using the error voltage.

Claims

1. A buck-boost regulator for converting an input voltage to an output voltage, comprising:

an inductor having a first end and a second end;

an error circuit which determines an error of the output voltage and which provides an error voltage indicative thereof;

a buck switching circuit which switches said first end of said inductor between the input voltage and ground as controlled by a buck pulse width modulation signal;

a buck ripple circuit which replicates ripple current through said inductor based on said buck pulse width modulation signal and which provides a buck ripple voltage indicative thereof;

a buck hysteretic comparator circuit which develops said buck pulse width modulation signal based on comparing said buck ripple voltage within a buck window voltage range between said error voltage and said error voltage combined with a buck window voltage;

a boost switching circuit which switches said second end of said inductor between the output voltage and ground as controlled by a boost pulse width modulation signal;

a boost ripple circuit which replicates ripple current through said inductor based on said boost pulse width modulation signal and which provides a boost ripple voltage indicative thereof; and

a boost hysteretic comparator circuit which develops said boost pulse width modulation signal based on comparing said boost ripple voltage within a boost window voltage range between said error voltage and said error voltage combined with a boost window voltage.

2. The buck-boost regulator of claim 1, wherein said buck ripple circuit comprises:

a ripple capacitive circuit which develops said buck ripple voltage on a first node;

a second node providing a reference voltage indicative of the output voltage; and

a transconductance amplifier having a first input receiving a voltage indicative of the voltage of said first end of said inductor, a second input coupled to said second node, and an output coupled to said first node for providing a buck ripple current to said ripple capacitive circuit.

3. The buck-boost regulator of claim 2, wherein said ripple capacitive circuit comprises:

a ripple capacitor coupled between said first node and a third node;

a ripple resistor coupled between said first node and said third node; and

an offset voltage source coupled between ground and said third node.

4. The buck-boost regulator of claim 1, further comprising a clamp circuit coupled to said buck ripple voltage which prevents said buck ripple voltage from falling below a predetermined minimum voltage level.

5. The buck-boost regulator of claim 1, wherein said buck hysteretic comparator circuit comprises:

a combiner which combines said error voltage with said buck window voltage and which provides a hysteresis voltage indicative thereof;

a first comparator which compares said buck ripple voltage with said hysteresis voltage and which provides a reset signal indicative thereof;

a second comparator which compares said buck ripple voltage with said error voltage and which provides a set signal indicative thereof; and

a logic circuit which receives said set and reset signals and which toggles said buck pulse width modulation signal based on said set and reset signals.

6. The buck-boost regulator of claim 5, wherein said buck window circuit asserts said buck window voltage at a minimum voltage while the input voltage is below the output voltage and adjusts said buck window voltage proportional to the input voltage while the input voltage is at or above the output voltage.

7. The buck-boost regulator of claim 1, wherein said boost ripple circuit comprises:

a ripple capacitive circuit which develops said boost ripple voltage on a first node;

a second node which switches between a reference voltage indicative of the output voltage and ground based on said boost pulse width modulation signal; and

a transconductance amplifier having a first input receiving a voltage indicative of the input voltage, a second input coupled to said second node, and an output coupled to said first node for providing a boost ripple current to said ripple capacitive circuit.

8. The buck-boost regulator of claim 7, wherein said ripple capacitive circuit comprises:

a ripple capacitor coupled between said first node and a third node;

a ripple resistor coupled between said first node and said third node; and

an offset voltage source coupled between ground and said third node.

9. The buck-boost regulator of claim 1, further comprising a clamp circuit coupled to said boost ripple voltage which prevents said boost ripple voltage from rising above a predetermined maximum voltage level.

10. The buck-boost regulator of claim 1, wherein said boost hysteretic comparator circuit comprises:

a combiner which combines said error voltage with said boost window voltage and which provides a hysteresis voltage indicative thereof;

a first comparator which compares said boost ripple voltage with said hysteresis voltage and which provides a reset signal indicative thereof;

a second comparator which compares said boost ripple voltage with said error voltage and which provides a set signal indicative thereof; and

a logic circuit which receives said set and reset signals and which toggles said boost pulse width modulation signal based on said set and reset signals.

11. The buck-boost regulator of claim 10, wherein said boost window circuit asserts said boost window voltage at a minimum voltage while the input voltage is above the output voltage and adjusts said boost window voltage inversely proportional to the input voltage while the input voltage is at or below the output voltage.

12. The buck-boost regulator of claim 1, further comprising:

a current sense circuit coupled to said inductor which asserts said switch disable signal when said inductor current reaches a minimum level; and

a switch disable circuit which disables a switch of at least one of said buck and boost switching circuits while said switch disable signal is asserted during a diode emulation mode.

13. An electronic device, comprising:

a power source providing an input voltage which ranges between a minimum voltage and a maximum voltage;

a load which receives a regulated source voltage having a voltage level which is greater than said minimum voltage and less than said maximum voltage; and

a buck-boost regulator for converting said input voltage to said regulated source voltage, comprising;

an inductor having a first end and a second end;

an error circuit which determines an error of said regulated source voltage and which provides an error voltage indicative thereof;

a buck switching circuit which switches said first end of said inductor between said input voltage and ground as controlled by a buck pulse width modulation signal;

a buck ripple circuit which replicates ripple current through said inductor based on said buck pulse width modulation signal and which provides a buck ripple voltage indicative thereof;

a buck hysteretic comparator circuit which develops said buck pulse width modulation signal based on comparing said buck ripple voltage with said error voltage;

a boost switching circuit which switches said second end of said inductor between said regulated source voltage and ground as controlled by a boost pulse width modulation signal;

a boost ripple circuit which replicates ripple current through said inductor based on said boost pulse width modulation signal and which provides a boost ripple voltage indicative thereof; and

a boost hysteretic comparator circuit which develops said boost pulse width modulation signal based on comparing said boost ripple voltage with said error voltage.

14. The electronic device of claim 13, wherein:

said buck ripple circuit comprises;

a buck ripple capacitive circuit coupled to a first node which develops said buck ripple voltage on said first node;

a second node providing a reference voltage indicative of said regulated source voltage; and

a buck transconductance amplifier having a first input receiving a voltage indicative of the voltage of said first end of said inductor, a second input coupled to said second node, and an output coupled to said first node for providing a buck ripple current to said buck ripple capacitive circuit; and

wherein said boost ripple circuit comprises;

a boost ripple capacitive circuit coupled to a third node which develops said boost ripple voltage on said third node;

a fourth node which switches between said reference voltage and ground based on said boost pulse width modulation signal; and

a boost transconductance amplifier having a first input receiving a voltage indicative of said input voltage, a second input coupled to said fourth node, and an output coupled to said third node for providing a boost ripple current to said boost ripple capacitive circuit.

15. The electronic device of claim 14, further comprising a first clamp circuit coupled to said first node which prevents said buck ripple voltage from falling below a predetermined minimum voltage level, and a second clamp circuit coupled to said fourth node which prevents said boost ripple voltage from rising above a predetermined maximum voltage level.

16. The electronic device of claim 13, further comprising:

a buck window circuit which adjusts a buck window voltage based on said input voltage relative to said regulated source voltage;

a boost window circuit which adjusts a boost window voltage based on said input voltage relative to said regulated source voltage;

wherein said buck hysteretic comparator circuit adds said buck window voltage to said error voltage for determining a buck hysteretic window for comparing said buck ripple voltage; and

wherein said boost hysteretic comparator circuit adds said boost window voltage to said error voltage for determining a boost hysteretic window for comparing said boost ripple voltage.

17. The electronic device of claim 13, wherein said power source comprises a battery.

18. A method of controlling a buck-boost regulator which converts an input voltage to an output voltage, comprising:

switching a first end of an inductor between the input voltage and ground as controlled by a buck pulse width modulation signal;

switching a second end of the inductor between the output voltage and ground as controlled by a boost pulse width modulation signal;

determining an error of the output voltage and providing an error voltage indicative thereof;

replicating ripple current through the inductor based on the buck pulse width modulation signal and providing a buck ripple voltage indicative thereof;

replicating ripple current through the inductor based on the boost pulse width modulation signal and providing a boost ripple voltage indicative thereof;

comparing the buck ripple voltage within a buck window voltage range and providing the buck pulse width modulation signal indicative thereof, wherein the buck window voltage range comprises a first voltage range between the error voltage and the error voltage combined with a buck window voltage; and

comparing the boost ripple voltage within a boost window voltage range and providing the boost pulse width modulation signal indicative thereof, wherein the boost window voltage range comprises a second voltage range between the error voltage and the error voltage combined with a boost window voltage.

19. The method of claim 18, wherein:

said replicating ripple current through the inductor based on the buck pulse width modulation signal and providing a buck ripple voltage indicative thereof comprises;

comparing a voltage indicative of the voltage at the first end of the inductor with a reference voltage indicative of the output voltage and converting to a buck ripple current indicative thereof; and

charging a buck ripple capacitor with the buck ripple current;

switching a first node between the reference voltage and ground based on the boost pulse width modulation signal; and

wherein said replicating ripple current through the inductor based on the boost pulse width modulation signal and providing a boost ripple voltage indicative thereof comprises;

comparing a voltage indicative of the input voltage with the voltage of the first node and converting to a boost ripple current indicative thereof; and

charging a boost ripple capacitor with the boost ripple current.

20. The method of claim 18, further comprising:

adjusting the buck window voltage based on a voltage difference between the input voltage and the output voltage; and

adjusting the boost window voltage based on the voltage difference.

21. The method of claim 18, further comprising:

detecting the current through the inductor falling to a minimum current level; and

disabling at least one of said switching a first end of the inductor and switching a second end of the inductor while the current through the inductor remains at the minimum current level during a diode emulation mode.