Circuit with enhanced mode and normal mode

• US 8,018,252 B2
• Filed: 08/25/2009
• Issued: 09/13/2011
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Robert Paul Masleid, Vatsal Dholabhai
• Original Assignee: Robert Paul Masleid, Vatsal Dholabhai
• Inventors: Dholabhai, Vatsal, Masleid, Robert Paul
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/546,960
• Publication Number:
  US 20090309631A1
• Time in Patent Office: 749 Days
• Field of Search: 326/86, 326/23, 326/27, 326/31, 326/34
• US Class Current: 326/86
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H04L 25/242 with retiming

Abstract

Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Claims

1. A circuit comprising:

a keeper circuit;

a first circuit coupled to said keeper circuit;

a second circuit coupled to said keeper circuit; and

a plurality of switches operable in a first position and operable in a second position, wherein said switches if operated in said first position configure said keeper circuit, said first circuit, and said second circuit into an enhanced mode and enable a portion of said first and second circuits, and wherein said switches if operated in said second position configure said keeper circuit, said first circuit, and said second circuit into a normal mode and disable said portion of said first and second circuits.

2. The circuit of claim 1, wherein said first circuit comprises:

a NAND gate including an output;

an output p-type transistor device coupled to said output of said NAND gate;

an upper delay circuit coupled to said output of said NAND gate; and

an upper half latch circuit coupled to said upper delay circuit and said NAND gate.

3. The circuit of claim 1, wherein said second circuit comprises:

a NOR gate including an output;

an output n-type transistor device coupled to said output of said NOR gate;

a lower delay circuit coupled to said output of said NOR gate; and

a lower half latch circuit coupled to said lower delay circuit and said NOR gate.

4. The circuit of claim 1, wherein said switches include a first plurality of switches connected to said first circuit and a second plurality of switches connected to said second circuit, and wherein said keeper circuit comprises:

a first inverter, a second inverter, a third inverter, and a fourth inverter arranged in series.

5. A circuit comprising:

an input node;

a keeper circuit;

a first circuit coupled to said input node and coupled to said keeper circuit;

a second circuit coupled to said input node and coupled to said keeper circuit, wherein a falling edge at said input node resets said first circuit, and wherein a rising edge at said input node resets said second circuit; and

a plurality of switches if operated in a first position configure said keeper circuit, said first circuit, and said second circuit into an enhanced mode, and wherein said switches if operated in a second position configure said keeper circuit, said first circuit, and said second circuit into a normal mode.

6. The circuit of claim 5, wherein said first circuit comprises:

a NAND gate including an output;

an output p-type transistor device coupled to said output of said NAND gate;

an upper delay circuit coupled to said output of said NAND gate; and

an upper half latch circuit coupled to said upper delay circuit and said NAND gate.

7. The circuit of claim 6, wherein said upper delay circuit comprises a first long delay circuit and a first short delay circuit.

8. The circuit of claim 5, wherein said second circuit comprises:

a NOR gate including an output;

an output n-type transistor device coupled to said output of said NOR gate;

a lower delay circuit coupled to said output of said NOR gate; and

a lower half latch circuit coupled to said lower delay circuit and said NOR gate.

9. The circuit of claim 8, wherein said lower delay circuit comprises a second long delay circuit and a second short delay circuit.

10. The circuit of claim 5, wherein said keeper circuit comprises:

a first inverter, a second inverter, a third inverter, and a fourth inverter arranged in series.

11. A circuit comprising:

an input node;

a first circuit coupled to said input node;

a second circuit coupled to said input node; and

a plurality of switches operable in a first position and operable in a second position, wherein said switches if operated in said first position enable an enhanced mode and enable a portion of said first and second circuits, wherein said switches if operated in said second position enable a normal mode and disable said portion of said first and second circuits,

wherein said first and second positions of said switches are independent of a value at said input node.

12. The circuit of claim 11 further comprising:

a keeper circuit coupled to said first and second circuits, wherein a falling edge at said input node resets said first circuit, and wherein a rising edge at said input node resets said second circuit.

13. The circuit of claim 12, wherein said first circuit comprises:

a NAND gate including an output;

an output p-type transistor device coupled to said output of said NAND gate;

an upper delay circuit coupled to said output of said NAND gate; and

an upper half latch circuit coupled to said upper delay circuit and said NAND gate.

14. The circuit of claim 13, wherein said upper delay circuit comprises a first long delay circuit and a first short delay circuit.

15. The circuit of claim 14, wherein said first long delay circuit comprises at least one inverter, and wherein said first short delay circuit comprises at least one inverter.

16. The circuit of claim 12, wherein said second circuit comprises:

a NOR gate including an output;

an output n-type transistor device coupled to said output of said NOR gate;

a lower delay circuit coupled to said output of said NOR gate; and

a lower half latch circuit coupled to said lower delay circuit and said NOR gate.

17. The circuit of claim 16, wherein said lower delay circuit comprises a second long delay circuit and a second short delay circuit.

18. The circuit of claim 17, wherein said second long delay circuit comprises at least one inverter, and wherein said second short delay circuit comprises at least one inverter.

19. The circuit of claim 12, wherein said switches include a first plurality of switches connected to said first circuit and a second plurality of switches connected to said second circuit, and wherein said keeper circuit comprises:

a first inverter, a second inverter, a third inverter, and a fourth inverter arranged in series.

20. A method comprising:

configuring a plurality of switches coupled to a driver circuit into a first mode to generate a driver circuit output which includes an enhanced characteristic and to enable a portion of a first circuit and a second circuit of said driver circuit; and

configuring said plurality of switches coupled to said driver circuit into a second mode to generate said driver circuit output which includes a normal characteristic and to disable said portion of said first circuit and said second circuit of said driver circuit,

wherein said enhanced and normal characteristics of said driver circuit output are independent of an input signal.

21. The method of claim 20, wherein said switches include a first plurality of switches connected to said first circuit and a second plurality of switches connected to said second circuit, and wherein said driver circuit further comprises:

a keeper circuit coupled to said first and second circuits.

22. The method of claim 21, wherein said first circuit comprises:

a NAND gate including an output;

an output p-type transistor device coupled to said output of said NAND gate;

an upper delay circuit coupled to said output of said NAND gate; and

an upper half latch circuit coupled to said upper delay circuit and said NAND gate.

23. The method of claim 21, wherein said second circuit comprises:

a NOR gate including an output;

an output n-type transistor device coupled to said output of said NOR gate;

a lower delay circuit coupled to said output of said NOR gate; and

a lower half latch circuit coupled to said lower delay circuit and said NOR gate.

24. The method of claim 21, wherein said keeper circuit comprises:

a first inverter, a second inverter, a third inverter, and a fourth inverter arranged in series.