Texture caching arrangement for a computer graphics accelerator

• US 8,018,467 B2
• Filed: 06/20/2005
• Issued: 09/13/2011
• Est. Priority Date: 03/22/1999
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Dawallu, Kioumars Kevin, Solanki, Gopal
• Primary Examiner(s): NGUYEN, HAU H
• Application Number:
  US11/158,638
• Publication Number:
  US 20050231519A1
• Time in Patent Office: 2,276 Days
• Field of Search: 345/503, 345/552, 345/557, 345/582
• US Class Current: 345/582
• CPC Class Codes: G06T 15/04 Texture mapping

Abstract

A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Claims

1. A computer comprising:

a central processing unit;

a bus;

memory for storing texels that are accessed using texture memory addresses; and

a graphics accelerator including;

a processor for generating pixel data, including texture coordinates for a texture to be mapped to a surface for display, for a plurality of pixels during a single clock interval;

a circuit for translating the texture coordinates into a texture memory address of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;

the texture cache for storing a portion of the texels that are stored in the memory, wherein the portion of the texels are accessed using the texture cache address and are used in generating texture values;

a buffer for storing requests for texels corresponding to pixels for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and

a circuit for generating texture values from texels to map the texture to pixels describing the surface for display.

2. A computer as claimed in claim 1 in which the texture cache includes a controller providing the replacement policy for replacing texels in the texture cache.

3. A computer as claimed in claim 1 further comprising

texture cache accessing circuitry,

texture cache miss generating circuitry,

memory accessing circuitry responsive to a texture cache miss for writing missing texels to the texture cache.

4. A computer as claimed in claim 1 wherein one of the texel flags is changed when a texel not stored in the texture cache is written to the texture cache.

5. A computer as claimed in claim 1 in which the buffer comprises a plurality of buffer stages for storing requests for texture values for pixels, wherein the plurality of buffer stages is sufficient to store the requests for texels while a miss is processed to read texels not stored in the texture cache from the memory.

6. A computer as claimed in claim 1 in which the circuit for accessing texels in response to requests for texture values corresponding to pixels responds to a plurality of requests in the single clock interval.

7. The computer as claimed in claim 1, wherein the texture cache is sized to store texels defining the texture over an entire triangle.

8. The computer as claimed in claim 1, wherein the texture cache is sized to store texels defining the texture over two typical triangles.

9. The computer as claimed in claim 1, wherein the texture cache maintains the positional relationship of the texels in a plane of the texture and the texture cache is accessed in two dimensions using the texture coordinates.

10. A method for generating texture values comprising the steps of:

storing texels in a memory that is accessed using texture memory addresses;

generating pixel data, including texture coordinates for a texture to be mapped to a surface for display, for a plurality of pixels during a single clock interval;

translating the texture coordinates into a texture memory address of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;

storing a portion of the texels that are used in generating texture values in the texture cache that is accessed using the texture cache address;

buffering requests for texels corresponding to pixels in a buffer for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and

generating the texture values from texels to map the texture to pixels describing the surface for display.

11. A method as claimed in claim 10 further comprising changing one of the texel flags when a texel not stored in the texture cache is written to the texture cache.

12. A method as in claim 10 further including processing a miss request for a texel not stored in the texture cache by reading the texel from the memory using the texture memory address.

13. The method as claimed in claim 10, wherein the texture cache is sized to store texels defining the texture over an entire triangle.

14. The method as claimed in claim 10, wherein the texture cache is sized to store texels defining the texture over two typical triangles.

15. The method as claimed in claim 10, wherein the texture cache maintains the positional relationship of the texels in a plane of the texture and the texture cache is accessed in two dimensions using the texture coordinates.

16. A graphics accelerator comprising:

a circuit for generating pixel data including texture coordinates for a texture to be mapped to a surface for display,

a circuit for translating the texture coordinates into a texture memory address used to access a memory storing texels of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;

the texture cache for storing a portion of the texels that are stored in the memory, wherein the texels are accessed using the texture cache address and are used in generating texture values;

a buffer for storing requests for texels corresponding to pixels for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and

a circuit for generating texture values from texels to map the texture to pixels describing the surface for display.

17. A graphics accelerator as claimed in claim 16 further comprising:

cache accessing circuitry,

cache miss generating circuitry,

memory accessing circuitry responsive to a texture cache miss for writing missing texels to the texture cache.

18. A graphics accelerator as claimed in claim 16 in which the buffer comprises a plurality of buffer stages for storing requests for texture values for pixels, wherein the plurality of buffer stages is sufficient to store the requests for texels while a miss is processed to read texels not stored in the texture cache from the memory.

19. The graphics accelerator as claimed in claim 16, wherein the texture cache is sized to store texels defining the texture over an entire triangle.

20. The graphics accelerator as claimed in claim 16, wherein the texture cache maintains the positional relationship of the texels in a plane of the texture and the texture cache is accessed in two dimensions using the texture coordinates.