Shift register circuit

• US 8,019,039 B1
• Filed: 07/15/2010
• Issued: 09/13/2011
• Est. Priority Date: 05/10/2010
• Status: Active Grant

• Current Assignee: Optronic Sciences LLC
• Original Assignee: AU Optronics Corporation
• Inventors: Tsai, Tsung-Ting
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US12/836,577
• Time in Patent Office: 425 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register includes plural shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes a pull-up unit, an input unit, an energy-store unit, a discharging unit and a pull-down unit. The pull-up unit pulls up a first gate signal according to a driving control voltage and a first clock. The input unit is utilized for inputting a second gate signal generated by a preceding shift register stage to become a driving control voltage which is stored in the energy-store unit. The discharging unit is utilized for performing an alternate pull-down operation on the driving control voltage according to a second clock and a third clock. The pull-down unit is utilized for performing an alternate pull-down operation on the first gate signal according to the second and third clocks.

Claims

1. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a driving control voltage and a first clock;

an input unit for inputting an (N−

1)th gate signal generated by an (N−

1)th shift register stage of the shift register stages to become the driving control voltage, wherein the input unit comprises a transistor having a first end electrically connected to the (N−

1)th shift register stage for receiving the (N−

1)th gate signal, a gate end for receiving a fourth clock, and a second end electrically connected to the pull-up unit;

an energy-store unit, electrically connected to the pull-up unit and the second end of the transistor, for storing the driving control voltage;

a discharging unit, electrically connected to the energy-store unit, for performing an alternate pull-down operation on the driving control voltage according to a second clock and a third clock; and

a pull-down unit, electrically connected to the Nth gate line, for performing an alternate pull-down operation on the Nth gate signal according to the second clock and the third clock;

wherein a high-level pulse of the first clock, a high-level pulse of the second clock, a high-level pulse of the third clock and a high-level pulse of the fourth clock are not overlapped to each other.

2. The shift register circuit of claim 1, wherein the energy-store unit comprises:

a capacitor electrically connected between the input unit and the Nth gate line.

3. The shift register circuit of claim 1, wherein the pull-up unit comprises a transistor, the transistor comprising:

a first end for receiving the first clock;

a gate end, electrically connected to the input unit, for receiving the driving control voltage; and

a second end electrically connected to the Nth gate line;

wherein the transistor is an N-type thin film transistor or an N-type field effect transistor.

4. The shift register circuit of claim 1,

wherein the transistor is an N-type thin film transistor or an N-type field effect transistor.

5. The shift register circuit of claim 1, wherein the input unit further comprises:

a capacitor electrically connected between the gate and second ends of the transistor.

6. The shift register circuit of claim 1, wherein:

the discharging unit comprises;

a first transistor comprising;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a first low power voltage; and

a second transistor comprising;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the first low power voltage; and

the pull-down unit comprises;

a third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving a second low power voltage greater than the first low power voltage; and

a fourth transistor comprising;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the second low power voltage;

wherein the first transistor, the second transistor, the third transistor and the fourth transistor are N-type thin film transistors or N-type field effect transistors.

7. The shift register circuit of claim 1, wherein:

the discharging unit comprises;

a first transistor comprising;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a low power voltage; and

a second transistor comprising;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the low power voltage; and

the pull-down unit comprises;

a third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving the low power voltage; and

a fourth transistor comprising;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the low power voltage;

wherein the first transistor, the second transistor, the third transistor and the fourth transistor are N-type thin film transistors or N-type field effect transistors.

8. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-down unit, electrically connected to an Nth gate line of the gate lines, for pulling down an Nth gate signal of the gate signals according to a driving control voltage and a first clock;

an input unit, for inputting an (N−

1)th gate signal generated by an (N−

1)th shift register stage of the shift register stages to become the driving control voltage, wherein the input unit comprises a transistor having a first end electrically connected to the (N−

1)th shift register stage for receiving the (N−

1)th gate signal, a gate end for receiving a fourth clock, and a second end electrically connected to the pull-down unit;

an energy-store unit, electrically connected to the pull-down unit and the second end of the transistor, for storing the driving control voltage;

a charging unit, electrically connected to the energy-store unit, for performing an alternate pull-up operation on the driving control voltage according to a second clock and a third clock; and

a pull-up unit, electrically connected to the Nth gate line, for performing an alternate pull-up operation on the Nth gate signal according to the second clock and the third clock;

wherein a low-level pulse of the first clock, a low-level pulse of the second clock, a low-level pulse of the third clock and a low-level pulse of the fourth clock are not overlapped to each other.

9. The shift register circuit of claim 8, wherein the energy-store unit comprises:

a capacitor electrically connected between the input unit and the Nth gate line.

10. The shift register circuit of claim 8, wherein the pull-down unit comprises a transistor, the transistor comprising:

a first end for receiving the first clock;

a gate end, electrically connected to the input unit, for receiving the driving control voltage; and

a second end electrically connected to the Nth gate line;

wherein the transistor is a P-type thin film transistor or a P-type field effect transistor.

11. The shift register circuit of claim 8,

wherein the transistor is a P-type thin film transistor or a P-type field effect transistor.

12. The shift register circuit of claim 8, wherein the input unit further comprises:

a capacitor electrically connected between the gate and second ends of the transistor.

13. The shift register circuit of claim 8, wherein:

the charging unit comprises;

a first transistor comprising;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a first high power voltage; and

a second transistor comprising;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the first high power voltage; and

the pull-up unit comprises;

a third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving a second high power voltage less than the first high power voltage; and

a fourth transistor comprising;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the second high power voltage;

wherein the first transistor, the second transistor, the third transistor and the fourth transistor are P-type thin film transistors or P-type field effect transistors.

14. The shift register circuit of claim 8, wherein:

the charging unit comprises;

a first transistor comprising;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a high power voltage; and

a second transistor comprising;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the high power voltage; and

the pull-up unit comprises;

a third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving the high power voltage; and

a fourth transistor comprising;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the high power voltage;

wherein the first transistor, the second transistor, the third transistor and the fourth transistor are P-type thin film transistors or P-type field effect transistors.

15. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a driving control voltage and a first clock;

an input unit, electrically connected to the pull-up unit and an (N−

1)th shift register stage of the shift register stages, for inputting an (N−

1)th gate signal generated by the (N−

1)th shift register stage to become the driving control voltage;

an energy-store unit, electrically connected to the pull-up unit and the input unit, for storing the driving control voltage;

a discharging unit for performing an alternate pull-down operation on the driving control voltage according to a second clock and a third clock, the discharging unit comprising;

a first transistor having;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a first low power voltage; and

a second transistor having;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the first low power voltage; and

a pull-down unit for performing an alternate pull-down operation on the Nth gate signal according to the second clock and the third clock, the pull-down unit comprising;

a third transistor having;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving a second low power voltage greater than the first low power voltage; and

a fourth transistor having;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the second low power voltage;

wherein a pulse rising edge of the first clock, a pulse rising edge of the second clock and a pulse rising edge of the third clock are sequentially staggered.

16. The shift register circuit of claim 15, wherein the first through fourth transistors are N-type thin film transistors or N-type field effect transistors.

18. The shift register circuit of claim 15, wherein the first through fourth transistors are P-type thin film transistors or P-type field effect transistors.

17. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

a pull-down unit, electrically connected to an Nth gate line of the gate lines, for pulling down an Nth gate signal of the gate signals according to a driving control voltage and a first clock;

an input unit, electrically connected to the pull-down unit and an (N−

1)th shift register stage of the shift register stages, for inputting an (N−

1)th gate signal generated by the (N−

1)th shift register stage to become the driving control voltage;

an energy-store unit, electrically connected to the pull-down unit and the input unit, for storing the driving control voltage;

a charging unit for performing an alternate pull-up operation on the driving control voltage according to a second clock and a third clock, the charging unit comprising;

a first transistor having;

a first end electrically connected to the energy-store unit;

a gate end for receiving the second clock; and

a second end for receiving a first high power voltage; and

a second transistor having;

a first end electrically connected to the first end of the first transistor;

a gate end for receiving the third clock; and

a second end for receiving the first high power voltage; and

a pull-up unit for performing an alternate pull-up operation on the Nth gate signal according to the second clock and the third clock, the pull-up unit comprising;

a third transistor comprising;

a first end electrically connected to the Nth gate line;

a gate end for receiving the second clock; and

a second end for receiving a second high power voltage less than the first high power voltage; and

a fourth transistor comprising;

a first end electrically connected to the first end of the third transistor;

a gate end for receiving the third clock; and

a second end for receiving the second high power voltage;

wherein a pulse falling edge of the first clock, a pulse falling edge of the second clock and a pulse falling edge of the third clock are sequentially staggered.