Lower power wake-up device
First Claim
1. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:
- a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal;
an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal;
a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T;
a clock that generates a clock signal having clock period in response to the threshold detector output signal T;
a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals; and
a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system.
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Accused Products
Abstract
A circuit producing a wake-up signal with a frequency selective RF amplifier that produces an amplified RF output. An RF detector detects the RF output and produces a signal W indicative of the the RF output signal'"'"'s presence. A threshold detector determines if the amplified output signal has reached a predetermined threshold and produces an output T. A clock signal is generated in response to the threshold detector output signal T. A data decoder logic circuit turns off the clock in the absence of an RF output signal for a time period and decodes the RF detector output W into a stream of output signals. A serial comparator compares a most recent stream of N output data from the data decoder logic with a stored reference to generate a wake-up signal that enables power to an electronic system. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
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Citations
23 Claims
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1. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:
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a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal; an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal; a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T; a clock that generates a clock signal having clock period in response to the threshold detector output signal T; a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals; and a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:
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a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal; an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal; a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T; a clock that generates a clock signal having clock period in response to the threshold detector output signal T; a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals; a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system; and wherein the clock is disabled either after a predetermined number of clock pulses from the clock since loss of the RF output signal or upon detection by the data decoder of a predetermined number of clock pulses from the clock since the output signal W indicates loss of the RF output signal, or upon detection by the data decoder of an invalid synchronization pattern. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:
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a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal; an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal; a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T; a clock that generates a clock signal having clock period in response to the threshold detector output signal T; a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals; a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system; wherein the system receives data from the serial comparator and in the presence of a valid data pattern, takes an action specified by the valid data pattern; and wherein the output data changes state whenever a specific number of clock pulses occur while the RF output signal is present. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification