Memory apparatus operable to perform a power-saving operation

• US 8,019,589 B2
• Filed: 10/30/2007
• Issued: 09/13/2011
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan, Smith, Michael John Sebastian
• Primary Examiner(s): PHAN, THAI Q
• Application Number:
  US11/929,320
• Publication Number:
  US 20080126692A1
• Time in Patent Office: 1,414 Days
• Field of Search: 703/23, 703/24, 365/185.09, 365/189.05, 711/105
• US Class Current: 703/24
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Claims

1. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of memory circuits on a registered dual in-line memory module (R-DIMM); and

one or more components electrically couplable to the host system, the one or more components being operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and one or more memory circuits of the plurality of memory circuits,

wherein each memory circuit of the plurality of memory circuits is electrically coupled to at least one of the one or more components, where the one or more components are further operable to identify at least one memory circuit of the plurality of memory circuits that is not being accessed; and

a chip on the R-DIMM operable to perform a power-saving operation on the at least one memory circuit identified as not being accessed.

2. The memory apparatus of claim 1, where the one or more components comprise a register or a buffer.

3. The memory apparatus of claim 1, where the simulated memory circuit presents a simulated control interface and a simulated data interface between the host system and the plurality of memory circuits.

4. The memory apparatus of claim 3, where the simulated control interface is configured to send and receive control, command, and clock signals, and the simulated data interface is configured to send and receive data signals.

5. The memory apparatus of claim 1, where the plurality of memory circuits comprise a stack of dynamic random access memory (DRAM) circuits on the R-DIMM.

6. The memory apparatus of claim 5, where the stack further includes the one or more components.

7. The memory apparatus of claim 1, where the power-saving operation comprises placing the at least one memory circuit identified as not being accessed in a precharge power down mode.

8. The memory apparatus of claim 7, where the one or more components are operable to place each memory circuit identified as not being accessed in a precharge power down mode by controlling a respective clock enable input of each memory circuit identified as not being accessed.

9. The memory apparatus of claim 1, where the one or more components are operable to identify the at least one memory circuit of the plurality of memory circuits as not being accessed based on how many pages are open in each respective memory circuit of the plurality of memory circuits.

10. The memory apparatus of claim 1, where the first components and second components are operable to perform the power saving operation by controlling a respective clock-enable pin of the at least one memory circuit identified as not being accessed.

11. The memory apparatus of claim 1, where the first components and second components are further operable to select one or more of the plurality of memory circuits by generating one or more chip select signals and to perform an operation on the one or more selected memory circuits.

12. A memory apparatus for use with a host system, the memory apparatus comprising:

an interface circuit; and

a plurality of memory circuits, each memory circuit of the plurality of memory circuits being electrically coupled to the interface circuit,

where the interface circuit is operable to present to the host system a simulated memory circuit, where there is a difference in at least one aspect between the simulated memory circuit and at least one of the plurality of memory circuits, and

where the interface circuit is further operable to identify at least one memory circuit of the plurality of memory circuits as not being accessed and to perform a power-saving operation on the at least one memory circuit identified as not being accessed.

13. The memory apparatus of claim 12, where the interface circuit includes one or more registers and one or more buffer chips,

where the one or more registers are operable to present a control interface between the host system and the plurality of memory circuits, and

where the one or more buffer chips are operable to present a data interface between the host system and the plurality of memory circuits.

14. The memory apparatus of claim 12, where the interface circuit comprises a plurality of components, the plurality of components including one or more registers and one or more buffers,

where the one or more registers are operable to present a control interface and an address interface between the host system and the plurality of memory circuits, and

where the one or more buffers are operable to present a data interface between the host system and the plurality of memory circuits.

15. The memory apparatus of claim 12, where the power-saving operation comprises placing the at least one memory circuit identified as not being accessed in a precharge power down mode.

16. The memory apparatus of claim 15, where the interface circuit is operable to place each memory circuit identified as not being accessed in a precharge power down mode by controlling a respective clock enable input of each memory circuit identified as not being accessed.

17. The memory apparatus of claim 12, where the interface circuit is operable to identify the at least one of the plurality of memory circuits as not being accessed based on how many pages are open in each respective memory circuit of the plurality of memory circuits.